Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems.

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm² and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µVrms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW.

A 4 µW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems.

We report an analog front-end prototype designed in 0.25 µm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 µW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 108 or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

A 8.6 µW 3-bit programmable gain amplifier for multiplexed-input neural recording systems.

We report a fully-integrated low-power 3-bit programmable-gain amplifier (PGA) that can be used as the second stage amplifier to adjust the gain for multi-channel neural recording systems. The design strategy maximizes energy-efficiency using a technique by optimizing a slew rate, gain and phase margin. The PGA consumes 8.66 µW from 1-V single supply. This is an order of magnitude lower than the previous designs reported up to date. Analysis, simulation, and measurement results will be described in detail for a part of a multiplexed 16-channels neural recording system. In this implementation, while giving a full flexibility of gain control, the overhead for each channel is quite negligible: only 0.54 µW in power and less than 0.002 mm(2) in area.

A 1.5V 120nW CMOS programmable monolithic reference generator for wireless implantable system.

We implement and characterize a 1.5 V 120 nW CMOS programmable monolithic reference generator for wireless implantable system. The proposed generator is optimized to be tolerable for power supply variation in a small area with programmability to generate various reference voltages and currents. The measured power line sensitivity are 0.02 / 1.1%/V for voltage and current reference, respectively. This reference generator can operate for input voltage ranging from 1.5 V to 3.5 V and implemented in an area of 0.011 mm(2), which is the smallest monolithic reference generator in 0.25 µm technology to the best of our knowledge. The output can vary from 20 nA to 33 nA for current reference and from 0.71 V to 1.03 V for voltage reference.

A low-power area-efficient 8 bit SAR ADC using dual capacitor arrays for neural microsystems.

We report an area-efficient 8bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680nW and the total chip area is 0.035 mm(2). We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 +/- 0.47 dB, 57.90 +/- 2.82dB, -53.58 +/- 2.15 dB, and 6.65 +/- 0.07 bits, respectively.

A 1microW 85nV/ radicalHz pseudo open-loop preamplifier with programmable band-pass filter for neural interface system.

We report an energy efficient pseudo open-loop amplifier with programmable band-pass filter developed for neural interface systems. The proposed amplifier consumes 400nA at 2.5V power supply. The measured thermal noise level is 85nV/ radicalHz and input-referred noise is 1.69microV(rms) from 0.3Hz to 1 kHz. The amplifier has a noise efficiency factor of 2.43, the lowest in the differential topologies reported up to date to our knowledge. By programming the switched-capacitor frequency and bias current, we could control the bandwidth of the preamplifier from 138 mHz to 2.2 kHz to meet various application requirements. The entire preamplifier including band-pass filters has been realized in a small area of 0.043mm(2) using a 0.25microm CMOS technology.