A Water-Resistant, Self-Healing Encapsulation Layer for a Stable, Implantable Wireless Antenna.

Polymers for implantable devices are desirable for biomedical engineering applications. This study introduces a water-resistant, self-healing fluoroelastomer (SHFE) as an encapsulation material for antennas. The SHFE exhibits a tissue-like modulus (approximately 0.4 MPa), stretchability (at least 450%, even after self-healing in an underwater environment), self-healability, and water resistance (WVTR result: 17.8610 g m-2 day-1). Further, the SHFE is self-healing in underwater environments via dipole-dipole interactions, such that devices can be protected from the penetration of biofluids and withstand external damage. With the combination of the SHFE and antennas designed to operate inside the body, we fabricated implantable, wireless antennas that can transmit information from inside the body to a reader coil that is outside. For antennas designed considering the dielectric constant, the uniformity of the encapsulation layer is crucial. A uniform and homogeneous interface is formed by simply overlapping two films. This study demonstrated the possibility of wireless communication in vivo through experiments on rodents for 4 weeks, maintaining the maximum communication distance (15 mm) without chemical or physical deformation in the SHFE layer. This study illustrates the applicability of fluoroelastomers in vivo and is expected to contribute to realizing the stable operation of high-performance implantable devices.

A Design of Analog Front-End with DBPSK Demodulator for Magnetic Field Wireless Network Sensors.

This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 mm2, 0.063 mm2, 0.045 mm2, and 0.03 mm2 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.

This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of -10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and -11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is -11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.

A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications.

This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed a synthesizable RTL-based CNN architecture for this purpose. The adopted technique of parallel computation of multiplication and accumulation (MAC) approach optimizes the hardware overhead by significantly reducing the arithmetic calculation and achieves instant results. While multiplier bank sharing throughout the convolutional operation with fully connected operation significantly reduces the implementation area. The CNN model is trained in MATLAB® on MNIST® handwritten dataset. For validation, the image pixel array from MNIST® handwritten dataset is applied on proposed RTL-based CNN architecture for biosensor applications in ModelSim®. The consistency is checked with multiple test samples and 92% accuracy is achieved. The proposed idea is implemented in 28 nm CMOS technology. It occupies 9.986 mm2 of the total area. The power requirement is 2.93 W from 1.8 V supply. The total time taken is 8.6538 ms.

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA.

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

2.4 GHz GaN HEMT Class-F Synchronous Rectifier Using an Independent Second Harmonic Tuning Circuit.

This paper proposes a class-F synchronous rectifier using an independent second harmonic tuning circuit for the power receiver of 2.4 GHz wireless power transmission systems. The synchronous rectifier can be designed by inverting the RF output port to the RF input port of the pre-designed class-F power amplifier based on time reversal duality. The design of the class-F power amplifier deploys an independent second harmonic tuning circuit in the matching networks to individually optimize the impedances of the fundamental and the second harmonic. The synchronous rectifier at the 2.4 GHz frequency is designed and implemented using a 6 W gallium nitride high electron mobility transistor (GaN HEMT). Peak RF-dc conversion efficiency of the rectifier of 69.6% is achieved with a dc output power of about 7.8 W, while the peak drain efficiency of the class-F power amplifier is 72.8%.

A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications.

This paper presents an adaptive control and communication protocol (ACCP) for the ultra-low power simultaneous wireless information and power transfer (SWIPT) system for sensor applications. The SWIPT system-related operations depend on harvested radio frequency (RF) energy from the ambient environment. The necessary power for SWIPT system operation is not always available and it depends on the available RF energy in the ambient environment, transmitted RF power from the SWIPT transmitter, and the distance from the transmitter and channel conditions. Thus, an efficient control and communication protocol is required which can control the SWIPT system for sensor applications which mainly consists of a transmitter and a receiver. Multiple data frame structures are used to optimize the exchange of bits for the communication and control of the SWIPT system. Both SWIPT transmitter and receiver are capable of using multiple modulation schemes which can be switched depending on the channel condition and the available RF energy in the ambient environment. This provides support for automatic switching between the time switching scheme and power splitting scheme for the distribution of received RF power in the SWIPT receiver. It also adjusts the digital clock frequency at the SWIPT receiver according to the harvested power level to optimize the power consumption. The SWIPT receiver controller with ACCP is implemented in 180 nm CMOS technology. The RF frequency of the SWIPT operation is 5.8 GHz. Digital clock frequency at the SWIPT receiver can be adjusted between 32 kHz and 2 MHz which provides data rates from 8 to 500 kbps, respectively. The power consumption and area utilization are 12.3 µW and 0.81 mm².

Design of a 900 MHz Dual-Mode SWIPT for Low-Power IoT Devices.

This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which a sensor node monitors the received power and adaptively controls the single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes the received radio frequency (RF) energy between the energy harvesting (EH) path and the information decoding (ID) path. The proposed SWIPT enables the self-powering of an ID transceiver above 20 dBm input power, leading to a battery-free network. The optimized PS ratio of 0.44 enables it to provide sufficient harvested energy for self-powering and energy-neutral operation of the ID transceiver. The ID transceiver can demodulate the amplitude-shift keying (ASK) and the binary phase-shift keying (BPSK) signals. Moreover, for low-input power level, a peak-to-average power ratio (PAPR) scheme based on multitone is also proposed for demodulation of the information-carrying RF signals. Due to the limited power, information is transmitted in uplink by backscatter modulation instead of RF signaling. To validate our proposed SWIPT architecture, a SWIPT printed circuit board (PCB) was designed with a multitone SWIPT board at 900 MHz. The demodulation of multitone by PAPR was verified separately on the PCB. Results showed the measured sensitivity of the SWIPT to be -7 dBm, and the measured peak power efficiency of the RF energy harvester was 69% at 20 dBm input power level. The power consumption of the injection-locked oscillator (ILO)-based phase detection path was 13.6 mW, and it could be supplied from the EH path when the input power level was high. The ID path could demodulate 4-ASK- and BPSK-modulated signals at the same time, thus receiving 3 bits from the demodulation process. Maximum data rate of 4 Mbps was achieved in the measurement.

A Low-Profile High-Gain and Wideband Log-Periodic Meandered Dipole Array Antenna with a Cascaded Multi-Section Artificial Magnetic Conductor Structure.

This paper presents a low-profile log-periodic meandered dipole array (LPMDA) antenna with wideband and high gain characteristics. The antenna consists of 14 dipole elements. For compactness, a meander line structure is applied to each dipole element to reduce its physical length. As a result, a compact and wideband LPMDA antenna is realized, exhibiting a wide impedance bandwidth of 1.04-5.22 GHz (ratio bandwidth of 5.02:1) for | S 11| < -10 dB. To enhance the antenna gain performance while maintaining the wideband behavior, the LPMDA antenna is integrated with a new design of an artificial magnetic conductor (AMC) structure. The designed AMC is realized by combining three AMC structures of different sizes to form a cascaded multi-section AMC structure, of which its overall operating bandwidth can continuously cover the entire impedance bandwidth of the LPMDA antenna. The proposed AMC-backed LPMDA antenna is experimentally verified and its measured -10 dB reflection bandwidth is found to be in the range of 0.84-5.15 GHz (6.13:1). At the main beam direction within the operating frequency bandwidth, the gain of the proposed AMC-backed LPMDA antenna ranges from 7.15-11.43 dBi, which is approximately 4 dBi higher than that of an LPMDA antenna without an AMC. Moreover, the proposed antenna has a low profile of only 0.138 λ L. ( λ L is the free-space wavelength at the lowest operating frequency).

5.8 GHz High-Efficiency RF-DC Converter Based on Common-Ground Multiple-Stack Structure.

This paper presents a 5.8 GHz RF-DC converter for high conversion efficiency and high output voltage based on a common-ground and multiple-stack structure. An RF isolation network (RFIN) for the multiple-stack RF-DC converter is proposed to combine the DC output voltage of each stack without separating its RF ground from the DC ground. The RFIN is designed using micro-strip transmission lines on a single-layer printed circuit board (PCB) with a common ground for the bottom plate. A 4-stack RF-DC converter based on a class-F voltage doubler for each stack was implemented to verify the proposed RFIN for the multiple-stack and common-ground structure. The performances of the implemented 4-stack RF-DC converter were evaluated in comparison to the single-stack converter that was also implemented. The size of the implemented 4-stack RF-DC converter using bare-chip Schottky diodes is 24 mm × 123 mm on a single-layer PCB. For an input power of 21 dBm for each stack of the RF-DC converter with a load resistance of 4 kΩ, a high efficiency of 73.1% and a high DC output voltage of 34.2 V were obtained.

A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is -95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

A 3-D Meandered Probe-Fed Dual-Band Circularly Polarized Dielectric Resonator Antenna.

A dual-band circularly polarized (CP) dielectric resonator antenna (DRA) designed on multi-layer substrates is proposed. An asymmetric C-shaped metallic strip is also incorporated into the upper side of the top substrate in the proposed design. The hexagonal dielectric resonator (DR) is excited by the proposed 3-D meandered probe, which generates multiple orthogonal TE-modes. It is found that the lower CP band arises due to the pair of fundamental modes of the hexagonal DR. In the upper CP band, pairs of higher broadside and even modes of the hexagonal DR are combined with a CP band that is induced by the asymmetric C-shaped metallic strip to yield a wide 3 dB axial ratio bandwidth (ARBW). A prototype of the proposed DRA is fabricated for experimental verification. The antenna exhibits a measured -10 dB reflection bandwidth of 56.43% (2.15⁻3.84 GHz). The far-field measurement shows measured 3 dB ARBWs of 7.56% (2.29⁻2.47 GHz) with a peak gain of 5.6 dBic and 16.47% (3.12⁻3.68 GHz) with a peak gain of 7.84 dBic in the lower and upper bands, respectively.

A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique.

In this paper, a high noise immunity, 28 × 16-channel finger touch sensing IC for an orthogonal frequency division multiplexing (OFDM) touch sensing scheme is presented. In order to increase the signal-to-noise ratio (SNR), the OFDM sensing scheme is proposed. The transmitter (TX) transmits the orthogonal signal to each channels of the panel. The receiver (RX) detects the magnitude of the orthogonal frequency to be transmitted from the TX. Due to the orthogonal characteristics, it is robust to narrowband interference and noise. Therefore, the SNR can be improved. In order to reduce the noise effect of low frequencies, a mixer and high-pass filter are proposed as well. After the noise is filtered, the touch SNR attained is 60 dB, from 20 dB before the noise is filtered. The advantage of the proposed OFDM sensing scheme is its ability to detect channels of the panel simultaneously with the use of multiple carriers. To satisfy the linearity of the signal in the OFDM system, a high-linearity mixer and a rail-to-rail amplifier in the TX driver are designed. The proposed design is implemented in 90 nm CMOS process. The SNR is approximately 60 dB. The area is 13.6 mm², and the power consumption is 62.4 mW.

Broadband Circularly Polarized Slot Antenna Loaded by a Multiple-Circular-Sector Patch.

In this paper, a microstrip-fed broadband circularly polarized (CP) slot antenna is presented. CP operation can be attained simply by embedding an S-shaped strip. By loading with a multiple-circular-sector patch, which consists of 12 circular-sector patches with identical central angles of 30° and different radii, the 3 dB axial ratio (AR) bandwidth is significantly broadened. To validate the performance of the proposed antenna, an antenna prototype is fabricated and tested. The fabricated antenna is 54 mm × 54 mm × 0.8 mm in size. The measured -10 dB reflection and 3 dB AR bandwidths are 81.06% (1.68⁻3.97 GHz) and 70.55% (1.89⁻3.95 GHz), respectively. Within the 3 dB AR bandwidth, the measured peak gain is 3.81 dBic. Reasonable agreement is also obtained between the measured and simulated results.

Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology.

In this paper, a low-power and small-area Single Edge Nibble Transmission (SENT) transmitter design is proposed for automotive pressure and temperature complex sensor applications. To reduce the cost and size of the hardware, the pressure and temperature information is processed with a single integrated circuit (IC) and transmitted at the same time to the electronic control unit (ECU) through SENT. Due to its digital nature, it is immune to noise, has reduced sensitivity to electromagnetic interference (EMI), and generates low EMI. It requires only one PAD for its connectivity with ECU, and thus reduces the pin requirements, simplifies the connectivity, and minimizes the printed circuit board (PCB) complexity. The design is fully synthesizable, and independent of technology. The finite state machine-based approach is employed for area efficient implementation, and to translate the proposed architecture into hardware. The IC is fabricated in 1P6M 180 nm CMOS process with an area of (116 µm × 116 µm) and 4.314 K gates. The current consumption is 50 µA from a 1.8 V supply with a total 90 µW power. For compliance with AEC-Q100 for automotive reliability, a reverse and over voltage protection circuit is also implemented with human body model (HBM) electro-static discharge (ESD) of +6 kV, reverse voltage of -16 V to 0 V, over voltage of 8.2 V to 16 V, and fabricated area of 330 µm × 680 µm. The extensive testing, measurement, and simulation results prove that the design is fully compliant with SAE J2716 standard.

Vertical-Strip-Fed Broadband Circularly Polarized Dielectric Resonator Antenna.

A vertical-strip-fed dielectric resonator antenna exhibiting broadband circular polarization characteristics is presented. A broad 3 dB axial ratio bandwidth (ARBW) is achieved by combining multiple orthogonal modes due to the use of a special-shaped dielectric resonator. The proposed antenna is fabricated to evaluate its actual performance capabilities. The antenna exhibits a measured 3 dB ARBW of 44.2% (3.35-5.25 GHz), lying within a -10 dB reflection bandwidth of 82.7% (2.44-5.88 GHz). The measured peak gain within 3 dB ARBW is found to be 5.66 dBic at 4.8 GHz. The measured results are in good agreement with the simulated results.

A Wideband Circularly Polarized Antenna with a Multiple-Circular-Sector Dielectric Resonator.

This paper presents the design of a wideband circularly polarized antenna using a multiple-circular-sector dielectric resonator (DR). The DR is composed of twelve circular-sector DRs with identical central angles of 30 ∘ but with different radii. A genetic algorithm is utilized to optimize the radii of the twelve circular-sector DRs to realize wideband circular polarization. The proposed antenna is excited using an aperture-coupled feeding technique through a narrow rectangular slot etched onto the ground plane. An antenna prototype is experimentally verified. The measured -10 dB reflection and 3 dB axial ratio (AR) bandwidths are 31.39% (1.88-2.58 GHz) and 19.30% (2.06-2.50 GHz), respectively, covering the operating bands of the following systems: UMTS-2100 (2.145 GHz), WiMAX (2.3 GHz), and Wi-Fi (2.445 GHz). A measured peak gain of 7.65 dBic at 2.225 GHz and gain variation of less than 2.70 dBic within the measured 3 dB AR bandwidth are achieved. In addition, the radiation patterns of the proposed antenna are presented and discussed.

A Wideband Circularly Polarized Pixelated Dielectric Resonator Antenna.

The design of a wideband circularly polarized pixelated dielectric resonator antenna using a real-coded genetic algorithm (GA) is presented for far-field wireless power transfer applications. The antenna consists of a dielectric resonator (DR) which is discretized into 8 × 8 grid DR bars. The real-coded GA is utilized to estimate the optimal heights of the 64 DR bars to realize circular polarization. The proposed antenna is excited by a narrow rectangular slot etched on the ground plane. A prototype of the proposed antenna is fabricated and tested. The measured -10 dB reflection and 3 dB axial ratio bandwidths are 32.32% (2.62-3.63 GHz) and 14.63% (2.85-3.30 GHz), respectively. A measured peak gain of 6.13 dBic is achieved at 3.2 GHz.