Impedance-Readout Integrated Circuits for Electrical Impedance Spectroscopy: Methodological Review.

This review article provides a comprehensive overview of impedance-readout integrated circuits (ICs) for electrical impedance spectroscopy (EIS) applications. The readout IC, a crucial component of on-chip EIS systems, significantly affects key performance metrics of the entire system, such as frequency range, power consumption, accuracy, detection range, and throughput. With the growing demand for portable, wearable, and implantable EIS systems in the Internet-of-Things (IoT) era, achieving high energy efficiency while maintaining a wide frequency range, high accuracy, wide dynamic range, and high throughput has become a focus of research. Furthermore, to enhance the miniaturization and convenience of EIS systems, many emerging systems utilize two-electrode or dry electrode configurations instead of the conventional four-electrode configuration with wet electrodes for impedance measurement. In response to these trends, various technologies have been developed to ensure reliable operations even at two- or dry-electrode interfaces. This article reviews the principles, advantages, and disadvantages of techniques employed in state-of-the-art impedance-readout ICs, aiming to achieve high energy efficiency, wide frequency range, high accuracy, wide dynamic range, low noise, high throughput, and/or high input impedance. The thorough review of these advancements will provide valuable insights into the future development of impedance-readout ICs and systems for IoT and biomedical applications.

A Wireless and Wearable Body-Pressure-Monitoring System for the Prevention of Pressure-Induced Skin Injuries.

This article presents a wireless and wearable body-pressure-monitoring system for the on-site, real-time prevention of pressure injuries for immobilized patients. For the prevention of pressure-induced skin injuries, a wearable pressure sensor system is designed to monitor the pressure at multiple sites on the skin and to alert the danger of prolonged application of pressure on the skin with a pressure-time integral (PTI) algorithm. The wearable sensor unit is developed using a pressure sensor based on a liquid metal microchannel and integrated with a flexible printed circuit board that includes a thermistor-type temperature sensor. The wearable sensor unit array is connected to the readout system board for the transmission of measured signals to a mobile device or PC via Bluetooth communication. We evaluate the pressure-sensing performances of the sensor unit and the feasibility of the wireless and wearable body-pressure-monitoring system through an indoor test and a preliminary clinical test at the hospital. It is shown that the presented pressure sensor has high-quality performance with excellent sensitivity to detect both high and low pressure. The proposed system measures the pressure at bony sites on the skin for about six hours continuously without any disconnection or failure, and the PTI-based alarming system operates successfully in the clinical setup. The system measures the pressure applied to the patient and provides meaningful information from the measured data for early diagnosis and prevention of bedsores to doctors, nurses, and healthcare workers.

Battery-Free, Wireless, Cuff-Type, Multimodal Physical Sensor for Continuous Temperature and Strain Monitoring of Nerve.

Peripheral nerve injuries cause various disabilities related to loss of motor and sensory functions. The treatment of these injuries typically requires surgical operations for improving functional recovery of the nerve. However, capabilities for continuous nerve monitoring remain a challenge. Herein, a battery-free, wireless, cuff-type, implantable, multimodal physical sensing platform for continuous in vivo monitoring of temperature and strain from the injured nerve is introduced. The thin, soft temperature, and strain sensors wrapped around the nerve exhibit good sensitivity, excellent stability, high linearity, and minimum hysteresis in relevant ranges. In particular, the strain sensor integrated with circuits for temperature compensation provides reliable, accurate strain monitoring with negligible temperature dependence. The system enables power harvesting and data communication to wireless, multiple implanted devices wrapped around the nerve. Experimental evaluations, verified by numerical simulations, with animal tests, demonstrate the feasibility and stability of the sensor system, which has great potential for continuous in vivo nerve monitoring from an early stage to complete regeneration.

Battery-Free, Wireless, Ionic Liquid Sensor Arrays to Monitor Pressure and Temperature of Patients in Bed and Wheelchair.

Repositioning is a common guideline for the prevention of pressure injuries of bedridden or wheelchair patients. However, frequent repositioning could deteriorate the quality of patient's life and induce secondary injuries. This paper introduces a method for continuous multi-site monitoring of pressure and temperature distribution from strategically deployed sensor arrays at skin interfaces via battery-free, wireless ionic liquid pressure sensors. The wirelessly delivered power enables stable operation of the ionic liquid pressure sensor, which shows enhanced sensitivity, negligible hysteresis, high linearity and cyclic stability over relevant pressure range. The experimental investigations of the wireless devices, verified by numerical simulation of the key responses, support capabilities for real-time, continuous, long-term monitoring of the pressure and temperature distribution from multiple sensor arrays. Clinical trials on two hemiplegic patients confined on bed or wheelchair integrated with the system demonstrate the feasibility of sensor arrays for a decrease in pressure and temperature distribution under minimal repositioning.

A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping SAR ADC With Chopper-Based Passive High-Pass IIR Filtering for Direct Neural Recording.

This paper presents a PVT-robust error-feedback (EF) noise-shaping SAR (NS-SAR) ADC for direct neural-signal recording. For closed-loop bidirectional neural interfaces enabling the next generation neurological devices, a wide-dynamic-range neural recording circuit is required to accommodate stimulation artifacts. A recording structure using an NS-SAR ADC can be a good candidate because the high resolution and wide dynamic range can be obtained with a low oversampling ratio and power consumption. However, NS-SAR ADCs require an additional gain stage to obtain a well-shaped noise transfer function (NTF), and a dynamic amplifier is often used as the gain stage to minimize power overhead at the cost of vulnerability to PVT variations. To overcome this limitation, the proposed work reutilizes the capacitive-feedback amplifier, which is the analog front-end of the neural recording circuit, as a PVT-robust gain stage to achieve a reliable NS performance. In addition, a new chopper-based implementation of a passive high-pass IIR filter is proposed, achieving an improved NTF compared to prior EF NS-SAR ADCs. Fabricated in a 180-nm CMOS process, the proposed NS-SAR ADC consumes 4.3-µW power and achieves a signal-to-noise-and-distortion ratio (SNDR) of 71.7 dB and 82.7 dB for a bandwidth of 5 kHz and 300 Hz, resulting in a Schreier figure of merit (FOM) of 162.4 dB and 162.1 dB, respectively. Direct neural recording using the proposed NS-SAR ADC is demonstrated successfully in vivo, and also its tolerance against stimulation artifacts is validated in vitro.

An Intra-Body Power Transfer System With 1-mW Power Delivered to the Load and 3.3-V DC Output at 160-cm of on-Body Distance.

This paper presents an intra-body power transfer (IBPT) system that can deliver power greater than 1 mW across an on-body distance of 160 cm. A system simulation model is built for the characterization of the channel and optimization of the power transfer. Our system analysis and experimental validation demonstrate that 1 MHz is an optimal carrier frequency for IBPT in terms of power delivered to the load (PDL) and power efficiency (PE). Prototype TX and RX boards were built, and an IC was fabricated in a 180-nm CMOS process for the RX. The proposed RX IC consists of a voltage doubler (VD) and a charge pump (CP) to obtain a sufficiently high voltage conversion ratio (VCR). Among various rectifier topologies, the VD is the optimal topology for the power receiver front-end because the parasitic ground coupling capacitances, which inevitably exist in the IBPT system, act as an inherent input-coupling capacitance for the VD. The implemented VD utilizes a dynamic VTH compensation (DVC) for its diode components. Compared to the conventional static VTH compensation (SVC), DVC in the VD reduces the reverse leakage current of the diode, thus maximizing the power conversion efficiency (PCE) and VCR. In addition, the PDL is enhanced by inserting an inductor on the TX board. It reduces the backward-path impedance without increasing the RX volume, boosting the PDL by up to 9.9 times compared to the PDL without the inductor insertion. The proposed IBPT system delivers up to 178.8 µW of power at 11.7% of maximum power efficiency with 3.3-V DC output voltage and even 1.385 mW of power with the inductor insertion, supporting various biomedical wearable sensors, such as ECG sensor modules.

On-Chip Sinusoidal Signal Generators for Electrical Impedance Spectroscopy: Methodological Review.

This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material's impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform's frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

An Impedance Readout IC with Ratio-Based Measurement Techniques for Electrical Impedance Spectroscopy.

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 µW for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1°, respectively.

A Multimodal Neural-Recording IC With Reconfigurable Analog Front-Ends for Improved Availability and Usability for Recording Channels.

In this work, we present an 8-channel reconfigurable multimodal neural-recording IC, which provides improved availability and usability of recording channels in various experiment scenarios. Each recording channel changes its configuration depending on whether the channel is assigned to record voltage or current signal. As a result, although the total number of channels is fixed by design, the channels utilized for voltage and current recording can be set freely and optimally for given experiment targets, scenarios, and circumstances, maximizing the availability and usability of recording channels.The proposed concept was demonstrated by fabricating the IC using a standard 180-nm CMOS process.Using the IC, we successfully performed an in vivo experiment from the hippocampal area of a mouse brain. The measured input noise of the reconfigurable front-end is 4.75 µVrms at voltage-recording mode and 7.4 pArms at current-recording mode while consuming 5.72 µW/channel.

A Polar-Demodulation-Based Impedance-Measurement IC Using Frequency-Shift Technique With Low Power Consumption and Wide Frequency Range.

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- µm CMOS technology consumes the power of 756 µW while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 % and 1.9 °, respectively.

A Wireless Power and Data Transfer IC for Neural Prostheses Using a Single Inductive Link With Frequency-Splitting Characteristic.

This paper presents a frequency-splitting-based wireless power and data transfer IC that simultaneously delivers power and forward data over a single inductive link. For data transmission, frequency-shift keying (FSK) is utilized because the FSK modulation scheme supports continuous wireless power transmission without disruption of the carrier amplitude. Moreover, the link that manifests the frequency-splitting characteristic due to a close distance between coupled coils provides wide bandwidth for data delivery without degrading the quality factors of the coils. It results in large power delivery, high data rate, and high power transfer efficiency. The presented IC fabricated in a 180-nm BCD process simultaneously achieves up-to-115-mW wireless power delivery to the load and 2.5-Mb/s downlink data rate over the single inductive link. The measured overall power efficiency from the DC power supply at the transmitter module to the load at the receiver module reaches 56.7 % at its maximum, and the bit error rate is lower than 10 -6 at 2.5 Mb/s. As a result, the figure of merit (FoM) for data transmission is enhanced by 2 times, and the FoM for power delivery is improved by 38.7 times compared to prior state-of-the-arts using a single inductive link.

A Scalable Readout IC Based on Wideband Noise Cancelling for Full-Rate Scanning of High-Density Microelectrode Arrays.

This paper presents a highly scalable readout IC for high-density microelectrode arrays (MEAs). Although the recent development of large-scale high-density MEAs provides opportunities to achieve sub-cellular neural recording over a wide network area, it is challenging to implement the readout IC that can operate with such MEAs. The requirement of high-speed recording in large-scale arrays induces wideband-noise folding, which makes it challenging to achieve a good noise performance for high-fidelity neural recording. Moreover, for the wideband readout, the major noise contributor changes from the readout circuit to the cell-electrode interface. In this paper, we first show why the interface noise becomes the dominant noise source and elucidate its component that contributes the most: sealing resistance. Then, we propose a new readout circuit structure, which can effectively cancel the wideband interface noise. As a result, the signal-to-noise ratio of input neural spike signals is improved dramatically in all cell-attachment or sealing conditions. Particularly, it is shown that under weakly sealed conditions, the spikes can be detected only when the proposed wideband noise cancellation technique is applied.

A Neural Recording and Stimulation Chip with Artifact Suppression for Biomedical Devices.

This paper presents chip implementation of the integrated neural recording and stimulation system with stimulation-induced artifact suppression. The implemented chip consists of low-power neural recording circuits, stimulation circuits, and action potential detection circuits. These circuits constitute a closed-loop simultaneous neural recording and stimulation system for biomedical devices, and a proposed artifact suppression technique is used in the system. Moreover, this paper also presents the measurement and experiment results of the implemented 4-to-4 channel neural recording and stimulation chip with 0.18 µm CMOS technology. The function and efficacy of simultaneous neural recording and stimulation is validated in both in vivo and animal experiments.

Subthreshold electrical stimulation as a low power electrical treatment for stroke rehabilitation.

As a promising future treatment for stroke rehabilitation, researchers have developed direct brain stimulation to manipulate the neural excitability. However, there has been less interest in energy consumption and unexpected side effect caused by electrical stimulation to bring functional recovery for stroke rehabilitation. In this study, we propose an engineering approach with subthreshold electrical stimulation (STES) to bring functional recovery. Here, we show a low level of electrical stimulation boosted causal excitation in connected neurons and strengthened the synaptic weight in a simulation study. We found that STES with motor training enhanced functional recovery after stroke in vivo. STES was shown to induce neural reconstruction, indicated by higher neurite expression in the stimulated regions and correlated changes in behavioral performance and neural spike firing pattern during the rehabilitation process. This will reduce the energy consumption of implantable devices and the side effects caused by stimulating unwanted brain regions.

A Power-Efficient Radiation Sensor Interface with a Peak-Triggered Sampling Scheme for Mobile Dosimeters.

Radiation sensor interfaces for battery-powered mobile dosimeters must consume low power to monitor the amount of radiation exposure over a long period. This paper proposes a power-efficient radiation sensor interface using a peak-triggered sampling scheme. Since the peak of the analog-to-digital converter's (ADC's) input represents radiation energy, our ADC only operates around the peak value thanks to the proposed sampling scheme. Although our ADC operates with a high sampling frequency, this proposed sampling scheme reduces the power consumption of the sensor interface because of the reduced operation time of the ADC. Our sensor interface does not have signal distortion caused by a conventional shaper because the interface quantizes the peak value using the high sampling frequency instead of the shaper. When the radiation input occurs once every 10 µs, the power consumption of the ADC with the proposed sampling scheme is only about 21.5% of the ADC's power consumption when the ADC continuously operates. In this worst case, the fabricated radiation sensor interface in a 0.18-µm complementary metal-oxide-semiconductor (CMOS) process consumes only 1.11 mW.

Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy.

This paper presents a reconfigurable time-to-digital converter (TDC) used to quantize the phase of the impedance in electrical impedance spectroscopy (EIS). The TDC in the EIS system must handle a wide input-time range for analysis in the low-frequency range and have a high resolution for analysis in the high-frequency range. The proposed TDC adopts a coarse counter to support a wide input-time range and cascaded time interpolators to improve the time resolution in the high-frequency analysis without increasing the counting clock speed. When the same large interpolation factor is adopted, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. A reconfigurable time interpolation factor is adopted to maintain the phase resolution with reasonable measurement time. The fabricated TDC has a peak-to-peak phase error of less than 0.72° over the input frequency range from 1 kHz to 512 kHz and the phase error of less than 2.70° when the range is extended to 2.048 MHz, which demonstrates a competitive performance when compared with previously reported designs.

Smartphone-based multispectral imaging and machine-learning based analysis for discrimination between seborrheic dermatitis and psoriasis on the scalp.

For appropriate treatment, accurate discrimination between seborrheic dermatitis and psoriasis in a timely manner is crucial to avoid complications. However, when they occur on the scalp, differential diagnosis can be challenging using conventional dermascopes. Thus, we employed smartphone-based multispectral imaging and analysis to discriminate between them with high accuracy. A smartphone-based multispectral imaging system, suited for scalp disease diagnosis, was redesigned. We compared the outcomes obtained using machine learning-based and conventional spectral classification methods to achieve better discrimination. The results demonstrated that smartphone-based multispectral imaging and analysis has great potential for discriminating between these diseases.

A Sub- µW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression.

We present a fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities. A difference between two consecutive neural signals, ∆-neural signal, is sampled in each channel to reduce the full dynamic range and the required resolution of an analog-to-digital converter (ADC), enabling the whole analog chain to be operated at a 0.5-V supply. A set of multiple ∆-signals are stored in analog memory to extract the magnitude and frequency features of the incoming neural signals, which are utilized to discriminate spikes in these signals instantaneously after the acquisition in the analog domain. The energy- and area-efficient successive approximation ADC is implemented and only converts detected spikes, decreasing the power dissipation and the amount of neural data. A prototype 16-channel neural interface IC was fabricated using a 0.18-µm CMOS process, and each component in the analog front-end was fully characterized. We successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal. The prototype chip consumed 0.88 µW/channel at a 0.5-V supply for the recording and compressed about 89% of neural data, saving the power consumption and bandwidth in the system.

A novel smart navigation system for intramedullary nailing in orthopedic surgery.

This paper proposes a novel smart surgical navigation system for intramedullary nailing in orthopedic surgery. Using a handle-integrated laser guidance module, the system can target a drill insertion point onto skin, indicating an accurate target position to perpendicularly access an invisible distal hole. The proposed handle-integration-based fixation of the laser guidance module precisely defines the relative position of the module with respect to the distal hole. Consequently, unlike conventional systems, the proposed system can indicate the target insertion point without any help from bulky and costly external position-tracking equipment that is usually required for compensating disturbances generated by external impacts. After insertion, a correct drilling direction toward the distal hole is guided by real-time drilling angle measurement modules-one integrated with the nail handle and the other with the drill body. Each module contains a 9-axis inertial sensor and a Bluetooth communication device. These two modules work together to provide real-time drilling angle data, allowing calculation of the directional error toward the center of the distal hole in real time. The proposed system removes the need for fluoroscopy and provides a compact and cost-effective solution compared with conventional systems.

Enhancement of Interface Characteristics of Neural Probe Based on Graphene, ZnO Nanowires, and Conducting Polymer PEDOT.

In the growing field of brain-machine interface (BMI), the interface between electrodes and neural tissues plays an important role in the recording and stimulation of neural signals. To minimize tissue damage while retaining high sensitivity, a flexible and a smaller electrode with low impedance is required. However, it is a major challenge to reduce electrode size while retaining the conductive characteristics of the electrode. In addition, the mechanical mismatch between stiff electrodes and soft tissues creates damaging reactive tissue responses. Here, we demonstrate a neural probe structure based on graphene, ZnO nanowires, and conducting polymer that provides flexibility and low impedance performance. A hybrid Au and graphene structure was utilized to achieve both flexibility and good conductivity. Using ZnO nanowires to increase the effective surface area drastically decreased the impedance value and enhanced the signal-to-noise ratio (SNR). A poly[3,4-ethylenedioxythiophene] (PEDOT) coating on the neural probe improved the electrical characteristics of the electrode while providing better biocompatibility. In vivo neural signal recordings showed that our neural probe can detect clearer signals.