Transforaminal Endoscopic Lumbar Lateral Recess Decompression for Octogenarian Patients.

The incidence of radiculopathy due to lumbar spinal stenosis has been on the increase in the aging population. However, patients aged ≥ 80 years hesitate to undergo conventional open surgery under general anesthesia because of the risk of postoperative morbidity and adverse events. Therefore, less invasive surgical alternatives are required for the elderly or medically handicapped patients. Transforaminal endoscopic lumbar lateral recess decompression (TELLRD) may be helpful for those patients. This study aimed to demonstrate the efficacy of TELLRD for treating radiculopathy in octogenarian patients. A total of 21 consecutive octogenarian patients with lumbar foraminal stenosis underwent TELLRD between January 2017 and January 2021. The inclusion criterion was unilateral radiculopathy, which stemmed from lumbar lateral recess stenosis. The pain source was verified using imaging studies and selective nerve blocks. Full-scale lateral canal decompression was performed using a percutaneous transforaminal endoscopic approach under local anesthesia. We found the pain scores and functional status improved significantly during the 24-month follow-up period. The clinical improvement rate was 95.24% (20 of 21 patients) with no systemic complication. In conclusion, endoscopic lateral recess decompression via the transforaminal approach is practical for octogenarian patients.

Treatment Outcome of the Brain Metastases in Peri-Rolandic Area: Comparison Between Surgery and Stereotactic Radiosurgery.

BACKGROUND: Brain metastases of peri-Rolandic area is crucial as it directly impacts the quality of life for cancer patients. Surgery or stereotactic radiosurgery (SRS) is considered for peri-Rolandic brain metastases as for other brain metastases. However, the benefit of each treatment modality on functional outcome has not been clearly defined for this tumor. The purpose of this study is to compare the functional course of each treatment and to suggest an effective treatment for patients' quality of life. METHODS: Fifty-two patients who had undergone SRS or surgery for brain metastasis confirmed by enhanced MRI were enrolled retrospectively. Overall survival (OS), progression free survival (PFS), and functional outcomes were estimated using the Kaplan-Meier method, univariate, multivariate analysis, and Cox proportional hazards regression. RESULTS: Median OS and PFS were 13.3 months and 8.9 months in our study population. Treatment modalities were not significant factors for OS and PFS. Extracranial systemic cancer progression was significant factor for both parameters (p=0.030 for OS and p=0.040 for PFS). Median symptom improvement (improvement of at least 1 grade after surgery compared to preoperative state) time was significantly shorter in surgery group than in the SRS group (10.5 days vs. 37.5 days, p=0.034). CONCLUSION: Surgery for brain metastases can contribute to a positive quality of life for the remaining duration of the patient's life.

Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 µA/µm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).

Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage.

In this work, a capacitorless one-transistor embedded dynamic random-access memory based on a metal-oxide-semiconductor field-effect transistor with a double-polysilicon layer structure has been proposed and investigated using technology computer-aided design simulation. By using the grain boundary for hole storage, a higher sensing margin of 4.35 /µA//µm is achieved compared to that without using the grain boundary. Furthermore, the proposed device achieves a superior retention time of 555.77 /µs, which is reasonable from the viewpoint of its application in embedded systems (>100 /µs), even at a high temperature of 358 K. For higher device reliability, the effect of the grain boundary on the capacitorless one-transistor embedded dynamic random-access memory is analyzed with different trap distributions. The proposed capacitorless one-transistor embedded dynamic random-access memory cell exhibited superior reliability in terms of retention time (>100 /µs).

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary.

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances.

In this paper, we adopt the vertical core-shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the p-type MOSFET (pMOSFET). Through this variation, the asymmetry of the electrical characteristics between n-type MOSFET (nMOSFET) and pMOSFET nanowire is considerably compensated. The inverter using the proposed core-shell structure shows the improved CMOS logic inverter characteristics. For example, the core-shell CMOS logic inverter shows performances such as NML = 0.315 V, NMH = 0.312 V, τPHL of 8.7 ps, and τPHL of 21 ps at an operating voltage of VDD = 0.7 V.

Recessed-Gate GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistor Using a Dual Gate-Insulator Employing TiO2/SiN.

In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO2/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO2/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO2 gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO2 gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.3 V, a maximum drain current of 556 mA/mm, a low Ron, sp of 1.45 mΩ·cm², and a breakdown voltage of 631 V at an off-state current of 1 µA/mm with VGS = 0 V. We have confirmed that a normally-off recessed-gate AlGaN/GaN MIS-HEMT using a TiO2/SiN dual gate-insulator is a promising candidate for power electronic applications.

Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET.

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core-shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 µA/µm, off-state current (Ioff) of 1.09 × 10-12 A/µm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.

Analysis of Electrical Characteristics of InAlGaN/GaN-Based High Electron Mobility Transistors with AlGaN Back Barriers.

In this study, the effect of an AlGaN back-barrier on the electrical characteristics of InAlGaN/GaN high electron mobility transistors (HEMTs) was investigated. The dependence of the thickness and the Al composition of the AlGaN back-barrier on the off-state current (Ioff) of the devices was investigated. An InAlGaN/GaN HEMT with an Al0.1GaN back-barrier of thickness 20 nm exhibited lower Ioff because of the carrier confinement effect, which was caused by the back-barrier. The carrier confinement effect also improved the maximum output current density and the transconductance (gm). Thus, the obtained cut-off frequency (fT) and maximum oscillation frequency (fmax) values for the InAlGaN/GaN HEMT with the 20 nm thick AlGaN back-barrier were 2.6% and 13% higher than those without the AlGaN back-barrier. In addition, the impact of the buffer trap density and GaN channel thickness were evaluated. In the case of a thickness of 20 nm for the Al0.1GaN back-barrier, a low Ioff was maintained although the trap density in the buffer layer was changed. In addition, as the gate length (LGa) decreased to 50 nm, the InAlGaN/GaN HEMT with the 20 nm thick Al0.1GaN back-barrier achieved better Ioff characteristics, lower drain-induced barrier lowering (DIBL) of 85.8 mV/V, and subthreshold swing (S) of 269 mV/dec owing to a reduction in the short-channel effect.

Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs.

This paper report a junctionless fin-type field-effect-transistor based capacitorless dynamic random access memory using three-dimensional technology computer-aided design simulations. The proposed 1T-DRAM is made up of a silicon germanium storage region surrounding a silicon fin. When the two materials form a heterojunction, a potential well is formed by the band discontinuity which carriers can be stored. During the program operation, band-to-band tunneling and gate-induced drain leakage occur simultaneously due to the gate and drain bias. Because of these phenomena, the electron-hole pair occurs, and generated holes are stored in the storage region by potential well. The holes formed are positively charged within the storage region, which mitigates the depletion of the channel and improves the operating current. The proposed device realizes the memory operation by the difference of the operating current depending on the presence or absence of the stored holes. In this work, the device is analyzed and optimized in detail. The proposed 1T-DRAM shows excellent performance with a retention time of 161 ms based on 50% of the maximum data margin.