RESUMEN
Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-in-memory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal-ferroelectric-metal-insulator-semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal-oxide-semiconductor FET, leading to a large MW (â¼11 V), fast operation speed (<20 ns), and high endurance (â¼1011 cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.
RESUMEN
The effect of negative capacitance (NC), which can internally boost the voltage applied to a transistor, has been considered to overcome the fundamental Boltzmann limit of a transistor. To stabilize the NC effect, the dielectric (DE) must be integrated into a heterostructure with a ferroelectric (FE) film. However, in a multidomain hafnia, the charge boosting effect is reduced owing to a lowering of the depolarization field originating from the stray field at each domain, and simultaneously, the operating voltage increases owing to the voltage division at the DE. Here, we demonstrate core approaches to the gate stack of energy-efficient device technology using a transient NC. Electrical measurements of the transistor with imprinted antiferroelectric and high CDE/CFE structures exhibit low subthreshold slopes below 20 mV/dec, a low voltage operation of 0.5 V, a fast operation of 20 ns, hysteresis-free Id-Vg, and high endurance characteristics of 1012 cycles. We expect that this will lead to the rapid implementation of the NC effect in high-speed switching device applications with significantly improved energy efficiency.
RESUMEN
We present herewith a novel approach of equally thick AFE/FE (ZrO2/HZO) bilayer stack heterostructure films for achieving an equivalent oxide thickness (EOT) of 4.1 Å with a dielectric constant (κ) of 56 in complementary metal-oxide semiconductor (CMOS) compatible metal-ferroelectric-metal (MFM) capacitors using a high-pressure annealing (HPA) technique. The low EOT and high κ values were achieved by careful optimization of AFE/FE film thicknesses and HPA conditions near the morphotropic phase boundary (MPB) after field cycling effects. Stable leakage current density (J < 10-7 A/cm2 at ±0.8 V) was found at 3/3 nm bilayer stack films (κ = 56 and EOT = 4.1 Å) measured at room temperature. In comparison with previous work, our remarkable achievement stems from the interfacial coupling between FE and AFE films as well as a high-quality crystalline structure formed by HPA. Kinetically stabilized hafnia films result in a small grain size in bilayer films, leading to reducing the leakage current density. Further, a higher κ value of 59 and lower EOT of 3.4 Å were found at 333 K. However, stable leakage current density was found at 273 K with a high κ value of 53 and EOT of 3.85 Å with J < 10-7 A/cm2. This is the lowest recorded EOT employing hafnia and TiN electrodes that are compatible with CMOS, and it has important implications for future dynamic random access memory (DRAM) technology.