High-density via RRAM cell with multi-level setting by current compliance circuits.

In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one considers cells under the process variation effect. The improved stability and tightened distributions on its multi-level states on via RRAM have been successfully demonstrated.

CMOS compatible 2T pixel for on-wafer in-situ EUV detection.

A novel 2-transistor (2T) pixel EUV detector is proposed and demonstrated by advanced CMOS technology. The proposed 2T detector also exhibits high spectral range (< 267 nm) and spatial resolution (67 µm) with high stability and CMOS Compatibility. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D EUV flux distribution without any external power. The compact 2T EUV detector pixels arranged in a test array are capable of on-wafer recording the 2D EUV flux distribution without any external power. Through proper initialization process, EUV induced discharging mechanism is fully investigated and an EUV induced electron emission efficiency model is established. Finally, a 2D array for in-situ EUV detection is demonstrated to precisely reflect the pattern projected on the chip/wafer surface.

A study of hydrogen plasma-induced charging effect in EUV lithography systems.

In the extreme ultraviolet lithography system, EUV-induced hydrogen plasma charging effect is observed by in situ embedded micro-detector array. The 4k-pixel on-wafer array can detect and store the distributions of H2 plasma in each in-pixel floating gate for non-destructive off-line read. The local uniformity of H2 plasma intensity extracted by the threshold voltages on an array and its distributions across a wafer by the average bit cell current of MDAs provide insights into the detailed conditions inside advanced EUV lithography chambers.

Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology.

An on-wafer micro-detector for in situ EUV (wavelength of 13.5 nm) detection featuring FinFET CMOS compatibility, 1 T pixel and battery-less sensing is demonstrated. Moreover, the detection results can be written in the in-pixel storage node for days, enabling off-line and non-destructive reading. The high spatial resolution micro-detectors can be used to extract the actual parameters of the incident EUV on wafers, including light intensity, exposure time and energy, key to optimization of lithographic processes in 5 nm FinFET technology and beyond.

Multifunctional Ion-Sensitive Floating Gate Fin Field-Effect Transistor with Three-Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology.

A multifunctional ion-sensitive floating gate Fin field-effect transistor (ISFGFinFET) for hydrogen and sodium detection is demonstrated. The ISFGFinFET comprises a FGFET and a sensing film, both of which are used to detect and improve sensitivity. The sensitivity of the ISFGFinFET can be adjusted by modulating the coupling effect of the FG. A nanoseaweed structure is fabricated via glancing angle deposition (GLAD) technology to obtain a large sensing area to enhance the sensitivity for hydrogen ion detection. A sensitivity of 266 mV per pH can be obtained using a surface area of 3.28 mm2 . In terms of sodium ion detection, a calix[4]arene sensing film to monitor sodium ions, obtaining a Na+ sensitivity of 432.7 mV per pNa, is used. In addition, the ISFGFinFET demonstrates the functionality of multiple ions detection simultaneously. The sensor arrays composed of 3 × 3 pixels are demonstrated, each of which comprise of an FGFET sensor and a transistor. Furthermore, 16 × 16 arrays with a decoder and other peripheral circuits are constructed and simulated. The performance of the proposed ISFGFinFET is competitive with that of other state-of-the-art ion sensors.

Wide range detector of plasma induced charging effect for advanced CMOS BEOL processes.

This work proposed a modified plasma induced charging (PID) detector to widen the detection range, for monitoring the possible plasma damage across a wafer during advanced CMOS BEOL processes. New antenna designs for plasma induced damage patterns with extended capacitors are investigated. By adapting the novel PID detectors, the maximum charging levels of the detectors have been enhanced.

An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array.

As one of the most promising embedded non-volatile storage solutions for advanced CMOS modules, resistive random access memory's (RRAM) applications depend highly on its cyclability. Through detailed analysis, links have been found between noise types, filament configurations and the occurrence of reset failure during cycling test. In addition, a recovery treatment is demonstrated to restore the cyclability of RRAM. An early detection circuit for vulnerable cells in an array is also proposed for further improving the overall endurance of an RRAM array. Lifetime of RRAM can be extended to over 10 k cycles without fail bits in an array.

Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology.

A novel in situ imaging solution and detectors array for the focused electron beam (e-beam) are the first time proposed and demonstrated. The proposed in-tool, on-wafer e-beam detectors array features full FinFET CMOS logic compatibility, compact 2 T pixel structure, fast response, high responsivity, and wide dynamic range. The e-beam imaging pattern and detection results can be further stored in the sensing/storage node without external power supply, enabling off-line electrical reading, which can be used to rapidly provide timely feedback of the key parameters of the e-beam on the projected wafers, including dosage, accelerating energy, and intensity distributions.

Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes.

High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly proposed test patterns for evaluating the effect of plasma-induced charging effect on the integrity of IMD between closely placed metal lines. Strong correlations between the plasma charging intensities and damages found in IMD layers are found and analyzed comprehensively.

Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology.

In this work, we present a novel pH sensor using efficient laterally coupled structure enabled by Complementary Metal-Oxide Semiconductor (CMOS) Fin Field-Effect Transistor (FinFET) processes. This new sensor features adjustable sensitivity, wide sensing range, multi-pad sensing capability and compatibility to advanced CMOS technologies. With a self-balanced readout scheme and proposed corresponding circuit, the proposed sensor is found to be easily embedded into integrated circuits (ICs) and expanded into sensors array. To ensure the robustness of this new device, the transient response and noise analysis are performed. In addition, an embedded calibration operation scheme is implemented to prevent the proposed sensing device from the background offset from process variation, providing reliable and stable sensing results.

RTN and Annealing Related to Stress and Temperature in FIND RRAM Array.

In this work, an observation on random telegraph noise (RTN) signal in the read current of a FinFET dielectric RRAM (FIND RRAM) device is presented. The RTN signal of a FIND RRAM cell is found to change after the device being subjected to cycling stress. After undergoing cycling stress, RRAM cells have a stronger tendency to show more frequent and intense RTN signals. The increase of noise levels in FIND RRAM cells can be alleviated generally by high temperature anneal, and with this concept, an on chip annealing scheme is proposed and demonstrated.

A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model.

Variability in resistive random access memory cell has been one of the critical challenges for the development of high-density RRAM arrays. While the sources of variability during resistive switching vary for different transition metal oxide films, the stochastic oxygen vacancy generation/recombination is generally believed to be the dominant cause. Through analyzing experimental data, a stochastic model which links the subsequent switching characteristics with its initial states of contact RRAM cells is established. By combining a conduction network model and the trap-assisted tunneling mechanism, the impacts of concentration and distribution of intrinsic oxygen vacancies in RRAM dielectric film are demonstrated with Monte Carlo Simulation. The measurement data on contact RRAM arrays agree well with characteristics projected by the model based on the presence of randomly distributed intrinsic vacancies. A strong correlation between forming characteristics and initial states is verified, which links forming behaviors to preforming oxygen vacancies. This study provides a comprehensive understanding of variability sources in contact RRAM devices and a reset training scheme to reduce the variability behavior in the subsequent RRAM states.

Correction to: Charge Splitting In Situ Recorder (CSIR) for Real-Time Examination of Plasma Charging Effect in FinFET BEOL Processes.

CORRECTION: In the original publication [1] Fig. 3 was presented incorrect. The correct additional file has been included with this erratum and the original article has been updated to rectify this error.

Charge Splitting In Situ Recorder (CSIR) for Real-Time Examination of Plasma Charging Effect in FinFET BEOL Processes.

A novel device for monitoring plasma-induced damage in the back-end-of-line (BEOL) process with charge splitting capability is first-time proposed and demonstrated. This novel charge splitting in situ recorder (CSIR) can independently trace the amount and polarity of plasma charging effects during the manufacturing process of advanced fin field-effect transistor (FinFET) circuits. Not only does it reveal the real-time and in situ plasma charging levels on the antennas, but it also separates positive and negative charging effect and provides two independent readings. As CMOS technologies push for finer metal lines in the future, the new charge separation scheme provides a powerful tool for BEOL process optimization and further device reliability improvements.

Retention Model of TaO/HfO x and TaO/AlO x RRAM with Self-Rectifying Switch Characteristics.

A retention behavior model for self-rectifying TaO/HfO x - and TaO/AlO x -based resistive random-access memory (RRAM) is proposed. Trapping-type RRAM can have a high resistance state (HRS) and a low resistance state (LRS); the degradation in a LRS is usually more severe than that in a HRS, because the LRS during the SET process is limited by the internal resistor layer. However, if TaO/AlO x elements are stacked in layers, the LRS retention can be improved. The LRS retention time estimated by extrapolation method is more than 5 years at room temperature. Both TaO/HfO x - and TaO/AlO x -based RRAM structures have the same capping layer of TaO, and the activation energy levels of both types of structures are 0.38 eV. Moreover, the additional AlO x switching layer of a TaO/AlO x structure creates a higher O diffusion barrier that can substantially enhance retention, and the TaO/AlO x structure also shows a quite stable LRS under biased conditions.

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process.

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.