Performance of Spherical Quantum Well Down Converters in Solid State Lighting.

We report the color conversion performance of amber and red emitting quantum dots (QDs) on InGaN solid-state lighting (SSL) light emitting diode (LED) packages. Spherical quantum well (SQW) architectures (CdS/CdSe1-xSx/CdS) were prepared using a library of thio- and selenourea synthesis reagents and high throughput synthesis robotics. CdS/CdSe1-xSx QDs with narrow luminescence bands were coated with thick CdS shells (thickness = 1.6-7.5 nm) to achieve photoluminescence quantum yields (PLQY) up to 88% at amber and red emission wavelengths (λmax = 600-642 nm, FWHM < 45 nm). The photoluminescence from SQWs encapsulated in silicone and deposited on LED packages was monitored under accelerated aging conditions (oven temperature = 85 °C, relative humidity = 5-85%, blue optical power density = 3-45 W/cm2) by monitoring the red photon output over several hundred hours of continuous operation. The growth of a ZnS shell on the SQW surface increases the stability under long-term operation but also reduces the PLQY, especially of SQWs with thick CdS shells. The results illustrate that the outer ZnS shell layer is key to optimizing the PLQY and the long-term stability of QDs during operation on SSL packages.

Complementary symmetry nanowire logic circuits: experimental demonstrations and in silico optimizations.

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.