Antiferroelectric negative capacitance from a structural phase transition in zirconia.

Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectricity, respectively. However, the recently discovered antiferroelectrics of fluorite structure (HfO2 and ZrO2) are different: A non-polar phase transforms into a polar phase by spontaneous inversion symmetry breaking upon the application of an electric field. Here, we show that this structural transition in antiferroelectric ZrO2 gives rise to a negative capacitance, which is promising for overcoming the fundamental limits of energy efficiency in electronics. Our findings provide insight into the thermodynamically forbidden region of the antiferroelectric transition in ZrO2 and extend the concept of negative capacitance beyond ferroelectricity. This shows that negative capacitance is a more general phenomenon than previously thought and can be expected in a much broader range of materials exhibiting structural phase transitions.

Sidewall Slope Control of InP Via Holes for 3D Integration.

This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 µm for 3D integration. The process for the InP via holes utilizes a common SiO2 layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl2/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO2 layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO2 layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO2 selectivity with RF power.

Development of in-situ particle monitor with beam homogenizing module for enhancement of nanoparticle countering efficiency.

An in situ particle monitor (ISPM) was developed to measure the concentration of several hundred nanosized contaminant particles generated from the semiconductor process. It is difficult to measure particles below 300 nm owing to low sensitivity and reliability. To improve the sensitivity and reduce the uncertainty caused by the Gaussian distribution of laser, a beam homogenizing module was applied to transform the Gaussian beam into a flat-top beam by total internal reflection. The performance of the beam-homogenizing ISPM was evaluated by measuring standard polystyrene latex particles in vacuum. We analyzed the measurement efficiency by a comparative evaluation with a scanning mobility particle sizer. Following this, the count of particles generated from the exhaust line of a plasma-enhanced chemical vapor deposition process was measured for real-time process diagnosis.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

Material-Independent Nanotransfer onto a Flexible Substrate Using Mechanical-Interlocking Structure.

Nanowire-transfer technology has received much attention thanks to its capability to fabricate high-performance flexible nanodevices with high simplicity and throughput. However, it is still challenging to extend the conventional nanowire-transfer method to the fabrication of a wide range of devices since a chemical-adhesion-based nanowire-transfer mechanism is complex and time-consuming, hindering successful transfer of diverse nanowires made of various materials. Here, we introduce a material-independent mechanical-interlocking-based nanowire-transfer (MINT) method, fabricating ultralong and fully aligned nanowires on a large flexible substrate (2.5 × 2 cm2) in a highly robust manner. For the material-independent nanotransfer, we developed a mechanics-based nanotransfer method, which employs a dry-removable amorphous carbon (a-C) sacrificial layer between a vacuum-deposited nanowire and the underlying master mold. The controlled etching of the sacrificial layer enables the formation of a mechanical-interlocking structure under the nanowire, facilitating peeling off of the nanowire from the master mold robustly and reliably. Using the developed MINT method, we successfully fabricated various metallic and semiconductor nanowire arrays on flexible substrates. We further demonstrated that the developed method is well suited to the reliable fabrication of highly flexible and high-performance nanoelectronic devices. As examples, a fully aligned gold (Au) microheater array exhibited high bending stability (106 cycling) and ultrafast (∼220 ms) heating operation up to ∼100 °C. An ultralong Au heater-embedded cuprous-oxide (Cu2O) nanowire chemical gas sensor showed significantly improved reversible reaction kinetics toward NO2 with 10-fold enhancement in sensitivity at 100 °C.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

Low-temperature growth of layered molybdenum disulphide with controlled clusters.

Layered molybdenum disulphide was grown at a low-temperature of 350 °C using chemical vapour deposition by elaborately controlling the cluster size. The molybdenum disulphide grown under various sulphur-reaction-gas to molybdenum-precursor partial-pressure ratios were examined. Using spectroscopy and microscopy, the effect of the cluster size on the layered growth was investigated in terms of the morphology, grain size, and impurity incorporation. Triangular single-crystal domains were grown at an optimized sulphur-reaction-gas to molybdenum-precursor partial-pressure ratio. Furthermore, it is proved that the nucleation sites on the silicon-dioxide substrate were related with the grain size. A polycrystalline monolayer with the 100-nm grain size was grown on a nucleation site confined substrate by high-vacuum annealing. In addition, a field-effect transistor was fabricated with a MoS2 monolayer and exhibited a mobility and on/off ratio of 0.15 cm(2) V(-1) s(-1) and 10(5), respectively.

Optical properties of Si microwires combined with nanoneedles for flexible thin film photovoltaics.

A combined wire structure, made up of longer periodic Si microwires and short nanoneedles, was prepared to enhance light absorption using one-step plasma etching via lithographical patterning. The combined wire array exhibited light absorption of up to ~97.6% from 300 to 1100 nm without an anti-reflection coating. These combined wire arrays on a Si substrate were embedded into a transparent polymer. A large-scale wire-embedded soft film was then obtained by peeling the polymer-embedded wire portion from the substrate. Optically attractive features were present in these soft films, making them suitable for use in flexible silicon solar cell applications.