Physics-based bias-dependent compact modeling of 1/f noise in single- to few-layer 2D-FETs.

1/f noise is a critical figure of merit for the performance of transistors and circuits. For two-dimensional devices (2D-FETs), and especially for applications in the GHz range where short-channel FETs are required, the velocity saturation (VS) effect can result in the reduction of 1/f noise at high longitudinal electric fields. A new physics-based compact model has been for the first time introduced for single- to few-layer 2D-FETs in this study, precisely validating 1/f noise experiments for various types of devices. The proposed model mainly accounts for the measured 1/f noise bias dependence as the latter is defined by different physical mechanisms. Thus, analytical expressions are derived, valid in all regions of operation in contrast to conventional approaches available in the literature so far, accounting for carrier number fluctuation (ΔN), mobility fluctuation (Δµ) and contact resistance (ΔR) effects based on the underlying physics that rules these devices. The ΔN mechanism due to trapping/detrapping together with an intense Coulomb scattering effect dominates the 1/f noise from the medium to the strong accumulation region while Δµ has also been demonstrated to modestly contribute in the subthreshold region. ΔR can also be significant in a very high carrier density. The VS induced reduction of 1/f noise measurements at high electric fields was also remarkably captured by the model. The physical validity of the model can also assist in extracting credible conclusions when conducting comparisons between experimental data from devices with different materials or dielectrics.

Compact Modeling Technology for the Simulation of Integrated Circuits Based on Graphene Field-Effect Transistors.

The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.

Bias dependent variability of low-frequency noise in single-layer graphene FETs.

Low-frequency noise (LFN) variability in graphene transistors (GFETs) is for the first time researched in this work under both experimental and theoretical aspects. LFN from an adequate statistical sample of long-channel solution-gated single-layer GFETs is measured in a wide range of operating conditions while a physics-based analytical model is derived that accounts for the bias dependence of LFN variance with remarkable performance. LFN deviations in GFETs stem from the variations of the parameters of the physical mechanisms that generate LFN, which are the number of traps (N tr) for the carrier number fluctuation effect (ΔN) due to trapping/detrapping process and the Hooge parameter (α H) for the mobility fluctuations effect (Δµ). ΔN accounts for an M-shape of normalized LFN variance versus gate bias with a minimum at the charge neutrality point (CNP) as it was the case for normalized LFN mean value while Δµ contributes only near the CNP for both variance and mean value. Trap statistical nature of the devices under test is experimentally shown to differ from classical Poisson distribution noticed at silicon-oxide devices, and this might be caused both by the electrolyte interface in GFETs under study and by the premature stage of the GFET technology development which could permit external factors to influence the performance. This not fully advanced GFET process growth might also cause pivotal inconsistencies affecting the scaling laws in GFETs of the same process.

Understanding the bias dependence of low frequency noise in single layer graphene FETs.

This letter investigates the bias-dependent low frequency noise of single layer graphene field-effect transistors. Noise measurements have been conducted with electrolyte-gated graphene transistors covering a wide range of gate and drain bias conditions for different channel lengths. A new analytical model that accounts for the propagation of the local noise sources in the channel to the terminal currents and voltages is proposed in this paper to investigate the noise bias dependence. Carrier number and mobility fluctuations are considered as the main causes of low frequency noise and the way these mechanisms contribute to the bias dependence of the noise is analyzed in this work. Typically, normalized low frequency noise in graphene devices has been usually shown to follow an M-shape dependence versus gate voltage with the minimum near the charge neutrality point (CNP). Our work reveals for the first time the strong correlation between this gate dependence and the residual charge which is relevant in the vicinity of this specific bias point. We discuss how charge inhomogeneity in the graphene channel at higher drain voltages can contribute to low frequency noise; thus, channel regions nearby the source and drain terminals are found to dominate the total noise for gate biases close to the CNP. The excellent agreement between the experimental data and the predictions of the analytical model at all bias conditions confirms that the two fundamental 1/f noise mechanisms, carrier number and mobility fluctuations, must be considered simultaneously to properly understand the low frequency noise in graphene FETs. The proposed analytical compact model can be easily implemented and integrated in circuit simulators, which can be of high importance for graphene based circuits' design.