Exploiting Ambipolarity in Graphene Field-Effect Transistors for Novel Designs on High-Frequency Analog Electronics.

Exploiting ambipolar electrical conductivity based on graphene field-effect transistors has raised enormous interest for high-frequency (HF) analog electronics. Controlling the device polarity, by biasing the graphene transistor around the vertex of the V-shaped transfer curve, enables to redesign and highly simplify conventional analog circuits, and simultaneously to seek for multifunctionalities, especially in the HF domain. This study presents new insights for the design of different HF applications such as power amplifiers, mixers, frequency multipliers, phase shifters, and modulators that specifically leverage the inherent ambipolarity of graphene-based transistors.

Physics-based bias-dependent compact modeling of 1/f noise in single- to few-layer 2D-FETs.

1/f noise is a critical figure of merit for the performance of transistors and circuits. For two-dimensional devices (2D-FETs), and especially for applications in the GHz range where short-channel FETs are required, the velocity saturation (VS) effect can result in the reduction of 1/f noise at high longitudinal electric fields. A new physics-based compact model has been for the first time introduced for single- to few-layer 2D-FETs in this study, precisely validating 1/f noise experiments for various types of devices. The proposed model mainly accounts for the measured 1/f noise bias dependence as the latter is defined by different physical mechanisms. Thus, analytical expressions are derived, valid in all regions of operation in contrast to conventional approaches available in the literature so far, accounting for carrier number fluctuation (ΔN), mobility fluctuation (Δµ) and contact resistance (ΔR) effects based on the underlying physics that rules these devices. The ΔN mechanism due to trapping/detrapping together with an intense Coulomb scattering effect dominates the 1/f noise from the medium to the strong accumulation region while Δµ has also been demonstrated to modestly contribute in the subthreshold region. ΔR can also be significant in a very high carrier density. The VS induced reduction of 1/f noise measurements at high electric fields was also remarkably captured by the model. The physical validity of the model can also assist in extracting credible conclusions when conducting comparisons between experimental data from devices with different materials or dielectrics.

Compact Modeling Technology for the Simulation of Integrated Circuits Based on Graphene Field-Effect Transistors.

The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.