RESUMEN
We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance-voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.
RESUMEN
The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET). After post-deposition annealing (PDA) and SF6 plasma treatment, the hole mobility is improved. From low-frequency noise analysis, reduction of the trap density and noise level is observed in PDA- and SF6-plasma-treated devices. (100) sidewall-oriented FinFETs show a lower noise level because of fewer interface traps compared to (110) sidewall-oriented devices. SF6 plasma affects the interface traps, whereas PDA relatively more affects bulk oxide traps for RMG high-k last FinFET.
