High-Dimensional Physical Reservoir with Back-End-of-Line-Compatible Tin Monoxide Thin-Film Transistor.

This work demonstrates a physical reservoir using a back-end-of-line compatible thin-film transistor (TFT) with tin monoxide (SnO) as the channel material for neuromorphic computing. The electron trapping and time-dependent detrapping at the channel interface induce the SnO·TFT to exhibit fading memory and nonlinearity characteristics, the critical assets for physical reservoir computing. The three-terminal configuration of the TFT allows the generation of higher-dimensional reservoir states by simultaneously adjusting the bias conditions of the gate and drain terminals, surpassing the performances of typical two-terminal-based reservoirs such as memristors. The high-dimensional SnO TFT reservoir performs exceptionally in two benchmark tests, achieving a 94.1% accuracy in Modified National Institute of Standards and Technology handwritten number recognition and a normalized root-mean-square error of 0.089 in Mackey-Glass time-series prediction. Furthermore, it is suitable for vertical integration because its fabrication temperature is <250 °C, providing the benefit of achieving a high integration density.

Memristive Crossbar Array-Based Probabilistic Graph Modeling.

Modern graph datasets with structural complexity and uncertainties due to incomplete information or data variability require advanced modeling techniques beyond conventional graph models. This study introduces a memristive crossbar array (CBA)-based probabilistic graph model (C-PGM) utilizing Cu0.3Te0.7/HfO2/Pt memristors, which exhibit probabilistic switching, self-rectifying, and memory characteristics. C-PGM addresses the complexities and uncertainties inherent in structural graph data across various domains, leveraging the probabilistic nature of memristors. C-PGM relies on the device-to-device variation across multiple memristive CBAs, overcoming the limitations of previous approaches that rely on sequential operations, which are slower and have a reliability concern due to repeated switching. This new approach enables the fast processing and massive implementation of probabilistic units at the expense of chip area. In this study, the hardware-based C-PGM feasibly expresses small-scale probabilistic graphs and shows minimal error in aggregate probability calculations. The probability calculation capabilities of C-PGM are applied to steady-state estimation and the PageRank algorithm, which is implemented on a simulated large-scale C-PGM. The C-PGM-based steady-state estimation and PageRank algorithm demonstrate comparable accuracy to conventional methods while significantly reducing computational costs.

Vertically Stackable Ovonic Threshold Switch Oscillator Using Atomic Layer Deposited Ge0.6Se0.4 Film for High-Density Artificial Neural Networks.

Nanodevice oscillators (nano-oscillators) have received considerable attention to implement in neuromorphic computing as hardware because they can significantly improve the device integration density and energy efficiency compared to complementary metal oxide semiconductor circuit-based oscillators. This work demonstrates vertically stackable nano-oscillators using an ovonic threshold switch (OTS) for high-density neuromorphic hardware. A vertically stackable Ge0.6Se0.4 OTS-oscillator (VOTS-OSC) is fabricated with a vertical crossbar array structure by growing Ge0.6Se0.4 film conformally on a contact hole structure using atomic layer deposition. The VOTS-OSC can be vertically integrated onto peripheral circuits without causing thermal damage because the fabrication temperature is <400 °C. The fabricated device exhibits oscillation characteristics, which can serve as leaky integrate-and-fire neurons in spiking neural networks (SNNs) and coupled oscillators in oscillatory neural networks (ONNs). For practical applications, pattern recognition and vertex coloring are demonstrated with SNNs and ONNs, respectively, using semiempirical simulations. This structure increases the oscillator integration density significantly, enabling complex tasks with a large number of oscillators. Moreover, it can enhance the computational speed of neural networks due to its rapid switching speed.

Impact of operation voltage and NH3 annealing on the fatigue characteristics of ferroelectric AlScN thin films grown by sputtering.

This work investigates the impact of the magnitude of cycling voltage on the fatigue characteristics of 40 nm-thick AlScN ferroelectric thin film. The fatigue rate and the rejuvenation of remanent polarization vary with the cycling voltage. The primary fatigue mechanism is identified to be the interfacial layer formation and domain wall pinning at high and low cycling voltages, respectively. Additionally, annealing the film under the NH3 atmosphere decreases the fatigue rate and improves endurance by eliminating impurities in the film. The amount of trapped charges at the interface also decreases after NH3 annealing, leading to a reduction in leakage current. Furthermore, the ferroelectric performance of the AlScN film is not degraded after the thermal annealing at 900 °C under the NH3 environment, suggesting its robustness against the severe thermal budget. It is concluded that NH3 annealing is a promising method to address the reliability issue of the AlScN film.