Complementary symmetry nanowire logic circuits: experimental demonstrations and in silico optimizations.

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.

A 160-kilobit molecular electronic memory patterned at 10(11) bits per square centimetre.

The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced wires within a dynamic random access memory (DRAM) circuit. Modern DRAM circuits have 140 nm pitch wires and a memory cell size of 0.0408 mum(2). Improving integrated circuit technology will require that these dimensions decrease over time. However, at present a large fraction of the patterning and materials requirements that we expect to need for the construction of new integrated circuit technologies in 2013 have 'no known solution'. Promising ingredients for advances in integrated circuit technology are nanowires, molecular electronics and defect-tolerant architectures, as demonstrated by reports of single devices and small circuits. Methods of extending these approaches to large-scale, high-density circuitry are largely undeveloped. Here we describe a 160,000-bit molecular electronic memory circuit, fabricated at a density of 10(11) bits cm(-2) (pitch 33 nm; memory cell size 0.0011 microm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020. A monolayer of bistable, [2]rotaxane molecules served as the data storage elements. Although the circuit has large numbers of defects, those defects could be readily identified through electronic testing and isolated using software coding. The working bits were then configured to form a fully functional random access memory circuit for storing and retrieving information.

Silicon p-FETs from ultrahigh density nanowire arrays.

Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 10(18) cm-3. Top-gated 4-microm-wide Si nanowire p-FETs yielded low off-currents (approximately 10(-12) A), high on/off ratios (10(5)-10(6)), good on current values (30 microA/microm), high mobilities (approximately 100 cm2/V-s), and low subthreshold swing values (approximately 80 mV/decade between 10(-12) and 10(-10) A increasing to 200 mV/decade between 10(-10)-10(-8) A).

Circuit fabrication at 17 nm half-pitch by nanoimprint lithography.

High density metal cross bars at 17 nm half-pitch were fabricated by nanoimprint lithography. Utilizing the superlattice nanowire pattern transfer technique, a 300-layer GaAs/AlGaAs superlattice was employed to produce an array of 150 Si nanowires (15 nm wide at 34 nm pitch) as an imprinting mold. A successful reproduction of the Si nanowire pattern was demonstrated. Furthermore, a cross-bar platinum nanowire array with a cell density of approximately 100 Gbit/cm(2) was fabricated by two consecutive imprinting processes.

Nanoscale patterning of alkyl monolayers on silicon using the atomic force microscope.

Self-assembled monolayers (SAMs) of 1-alkenes on hydrogen-passivated silicon substrates were successfully patterned on the nanometer scale using an atomic force microscope (AFM) probe tip. Nanoshaving experiments on alkyl monolayers formed on H-Si(111) not only demonstrate the flexibility of this technique but also show that patterning with an AFM probe is a viable method for creating well-defined, nanoscale features in a monolayer matrix in a reproducible and controlled manner. Features of varying depths (2-15 nm) were created in the alkyl monolayers by controlling the applied load and the number of etching scans made at high applied loads. The patterning on these SAM films is compared with the patterning of alkyl siloxane monolayers on silicon and mica.