High-Performance P-Channel Tin Halide Perovskite Thin Film Transistor Utilizing a 2D-3D Core-Shell Structure.

Metal halide perovskites (MHPs) are plausible candidates for practical p-type semiconductors. However, in thin film transistor (TFT) applications, both 2D PEA2 SnI4 and 3D FASnI3 MHPs have different drawbacks. In 2D MHP, the TFT mobility is seriously reduced by grain-boundary issues, whereas 3D MHP has an uncontrollably high hole density, which results in quite a large threshold voltage (Vth ). To overcome these problems, a new concept based on a 2D-3D core-shell structure is herein proposed. In the proposed structure, a 3D MHP core is fully isolated by a 2D MHP, providing two desirable effects as follows. (i) Vth can be independently controlled by the 2D component, and (ii) the grain-boundary resistance is significantly improved by the 2D/3D interface. Moreover, SnF2 additives are used, and they facilitate the formation of the 2D/3D core-shell structure. Consequently, a high-performance p-type Sn-based MHP TFT with a field-effect mobility of ≈25 cm2 V-1 s-1 is obtained. The voltage gain of a complementary metal oxide semiconductor (CMOS) inverter comprising an n-channel InGaZnOx TFT and a p-channel Sn-MHP TFT is ≈200 V/V at VDD = 20 V. Overall, the proposed 2D/3D core-shell structure is expected to provide a new route for obtaining high-performance MHP TFTs.

Performance Enhancement of Pentacene-Based Organic Thin-Film Transistors Using a High-K PVA/Low-K PVP Bilayer as the Gate Insulator.

In this study, we proposed using the high-K polyvinyl alcohol (PVA)/low-K poly-4-vinylphenol (PVP) bilayer structure as the gate insulator to improve the performance of a pentacene-based organic thin-film transistor. The dielectric constant of the optimal high-K PVA/low-K PVP bilayer was 5.6, which was higher than that of the single PVP layer. It resulted in an increase in the gate capacitance and an increased drain current. The surface morphology of the bilayer gate dielectric could be suitable for pentacene grain growth because the PVP layer was deposited above the organic PVA surface, thereby replacing the inorganic surface of the ITO gate electrode. The device performances were significantly improved by using the bilayer gate dielectric based upon the high-K characteristics of the PVA layer and the enlargement of the pentacene grain. Notably, the field-effect mobility was increased from 0.16 to 1.12 cm2/(Vs), 7 times higher than that of the control sample.

High-Performance Indium Gallium Tin Oxide Transistors with an Al2O3 Gate Insulator Deposited by Atomic Layer Deposition at a Low Temperature of 150 °C: Roles of Hydrogen and Excess Oxygen in the Al2O3 Dielectric Film.

In this work, high-performance amorphous In0.75Ga0.23Sn0.02O (a-IGTO) transistors with an atomic layer-deposited Al2O3 dielectric layer were fabricated at a maximum processing temperature of 150 °C. Hydrogen (H) and excess oxygen (Oi) in the Al2O3 film, which was controlled by adjusting the oxygen radical density (PO2: flow rate of O2/[Ar+O2]) in the radio-frequency (rf) plasma during ALD growth of Al2O3, significantly affected the performance and stability of the resulting IGTO transistors. The concentrations of H and Oi in Al2O3/IGTO stacks according to PO2 were characterized by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, hard X-ray photoemission spectroscopy, and thermal desorption spectroscopy. The high concentration of H at a low PO2 of 2.5% caused heavy electron doping in the underlying IGTO during thermal annealing at 150 °C, leading to a conductive behavior in the resulting transistor without modulation capability. In contrast, a high PO2 condition of 20% introduced O2 molecules (or Oi) into the Al2O3 film, which negatively impacted the carrier mobility and caused anomalous photo-bias instability in the IGTO transistor. Through in-depth understanding of how to manipulate H and Oi in Al2O3 by controlling the PO2, we fabricated high-performance IGTO transistors with a high field-effect mobility (µFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V, and ION/OFF ratio of ∼109 even at the maximum processing temperature of 150 °C. Simultaneously, the optimized devices were resistant to exposure to external positive gate bias stress (PBS) and negative bias stress (NBS) for 3600 s, where the VTH shifts for exposure to PBS and NBS for this duration were 0.1 V and -0.15 V, respectively.

High-Entropy van der Waals Materials Formed from Mixed Metal Dichalcogenides, Halides, and Phosphorus Trisulfides.

The charge, spin, and composition degrees of freedom in a high-entropy alloy endow it with tunable valence and spin states, infinite combinations, and excellent mechanical performance. Meanwhile, the stacking, interlayer, and angle degrees of freedom in a van der Waals material bring to it exceptional features and technological applications. Integration of these two distinct material categories while keeping their merits would be tempting. On the basis of this heuristic thinking, we design and explore a new range of materials (i.e., dichalcogenides, halides, and phosphorus trisulfides) with multiple metallic constitutions and intrinsic layered structure, which are coined as high-entropy van der Waals materials. Millimeter-scale single crystals with a homogeneous element distribution can be efficiently acquired and easily exfoliated or intercalated in this materials category. Multifarious physical properties such as superconductivity, magnetic ordering, metal-insulator transition, and corrosion resistance have been exploited. Further research based on the concept of high-entropy van der Waals materials will enrich the high-throughput design of new systems with intriguing properties and practical applications.