A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory.

For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (VTH) characteristic via the single negative differential resistance (NDR) phenomenon. In particular, recent advances in forming van der Waals (vdW) heterostructures with two-dimensional crystals have opened up new possibilities for realizing such NDR-based tunneling devices. However, it has been challenging to exhibit three VTH through the multiple-NDR (m-NDR) phenomenon in a single device even by using vdW heterostructures. Here, we show the m-NDR device formed on a BP/(ReS2 + HfS2) type-III double-heterostructure. This m-NDR device is then integrated with a vdW transistor to demonstrate a ternary vdW latch circuit capable of storing three logic states. Finally, the ternary latch is extended toward ternary SRAM, and its high-speed write and read operations are theoretically verified.

Functionalized Organic Material Platform for Realization of Ternary Logic Circuit.

Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required to achieve a stable MVL operation. In this study, an organic NDR (ONDR) device with double-peak transfer characteristics and a high peak-to-valley current ratio (PVCR; >102) is fabricated by utilizing an organic material platform for the development of a key element device for MVL applications. The organic NDT (ONDT) device is fabricated using a series connection of electron-dominant (P(NDI2OD-Se2)) and hole-dominant (P(DPP2DT-T2)) channel ambipolar organic field-effect transistors (AOFETs), and the NDR feature is achieved via correlated biasing of the ONDT device. The PVCR of the ONDT device can reach up to 13,000 via carrier transfer modulation of the AOFETs by varying the PMMA:P(VDF-TrFE) ratio of the mixed layer that is used as the top-gate dielectric of each AOFET. Further, ternary latch circuit operation is demonstrated using the developed ONDR device that stores three logic states with three distinct and controllable output states by adjusting the PMMA:P(VDF-TrFE) ratio of the dielectric layer.