Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 µA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels.

In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV dec-1to 60 and 80 mV dec-1inp- andn-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s. In contrast, the SS value does not change even after a negative bias stress (NBS) is applied for 1000 s. The difference in the switching characteristics under PBS and NBS is attributed to the ability of the interface traps to readily gain electrons from the inversion layer. The switching characteristics deteriorated by PBS are completely recovered after annealing at 300 °C for 10 min, and the characteristics remain stable even after PBS is applied again for 1000 s.

Binarized neural network of diode array with high concordance to vector-matrix multiplication.

In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector-matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.