Carbon Nanotubes for Radiation-Tolerant Electronics.

Electronics for space applications have stringent requirements on both performance and radiation tolerance. The constant exposure to cosmic radiation damages and eventually destroys electronics, limiting the lifespan of all space-bound missions. Thus, as space missions grow increasingly ambitious in distance away from Earth, and therefore time in space, the electronics driving them must likewise grow increasingly radiation-tolerant. In this work, we show how carbon nanotube (CNT) field-effect transistors (CNFETs), a leading candidate for energy-efficient electronics, can be strategically engineered to simultaneously realize a robust radiation-tolerant technology. We demonstrate radiation-tolerant CNFETs by leveraging both extrinsic CNFET benefits owing to CNFET device geometries enabled by their low-temperature fabrication, as well as intrinsic CNFET benefits owing to CNTs' inherent material properties. By performing a comprehensive study and optimization of CNFET device geometries, we demonstrate record CNFET total ionizing dose (TID) tolerance (above 10 Mrad(Si)) and show transient upset testing on complementary metal-oxide-semiconductor (CMOS) CNFET-based 6T SRAM memories via X-ray prompt dose testing (threshold dose rate = 1.3 × 1010 rad(Si)/s). Taken together, this work demonstrates CNFETs' potential as a technology for next-generation space applications.

Modern microprocessor built from complementary carbon nanotube transistors.

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal-oxide-semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems.

ALD HfO2 Films for Defining Microelectrodes for Electrochemical Sensing and Other Applications.

Microelectrodes are used in a wide range of applications from analytical electrochemistry and biomolecular sensing to in vivo implants. While a variety of insulating materials have been used to define the microelectrode active area, most are not suitable for nanoscale electrodes (<1 µm2) due to the limited robustness of these films when the film thickness is on the order of the nanoelectrode dimension. In this study, we investigate atomic layer deposited hafnium dioxide (ALD HfO2) as an insulating film to coat planar platinum microelectrodes, with the active areas being defined where the HfO2 is etched. Thermally grown films with thicknesses between 10 and 60 nm were deposited by 100 to 550 ALD cycles and were initially characterized by measuring their standard electrical properties and imaging incipient texture development. Electrochemical measurements on the structures were made, including linear sweep voltammetry and electrochemical impedance spectroscopy, which identified the presence of pinholes in films deposited over the range of 100 to 350 cycles, resulting in leakage. These measurements also suggest a lower limit to the size of microelectrodes below which the electrochemical current detected is no longer dominated by that through the exposed active area. A bilayer insulator comprising ALD HfO2 coated with parylene-C was investigated to minimize the pinhole leakage. Steady-state currents were measured for different electrode areas, qualitatively agreeing with the theory for areas down to ∼1 µm2. For sub-square micrometer electrode areas, bilayer-insulated devices with parylene-C apertures that exposed the smallest microelectrode area showed measured currents that were consistent with extrapolations, indicating that it reduces leakage through HfO2.

Tunable n-Type Doping of Carbon Nanotubes through Engineered Atomic Layer Deposition HfOX Films.

Although digital systems fabricated from carbon-nanotube-based field-effect transistors (CNFETs) promise significant energy efficiency benefits, realizing these benefits requires a complementary CNFET technology, i.e., CNFET CMOS, comprising both PMOS and NMOS CNFETs. Furthermore, this CNFET CMOS process must be robust ( e.g., air-stable), tunable ( e.g., ability to control CNFET threshold voltages), and silicon CMOS compatible (to integrate within existing manufacturing facilities and process flows). Despite many efforts, such a silicon CMOS compatible CNT doping strategy for forming NMOS CNFETs does not exist. Techniques today are either not air-stable (using reactive low work function metals), not solid-state or silicon CMOS compatible (employing soluble molecular dopants in ionic solutions), or have not demonstrated precise control over the amount of doping (for setting threshold voltage,  VT). Here, we demonstrate an electrostatic doping technique that meets all of these requirements. The key to our technique is leveraging atomic layer deposition (ALD) to encapsulate CNTs with nonstoichiometric oxides. We show that ALD allows for precise control of oxide stoichiometry, which translates to direct control of the amount of CNT doping. We experimentally demonstrate the ability to modulate the strength of the p-type conduction branch by >2500× (measured as the change in current at fixed bias), realize NMOS CNFETs with n-type conduction ∼500× stronger than p-type conduction (also measured by the relative current at fixed biases), and tune VT over a ∼1.5 V range. Moreover, our technique is compatible with other doping schemes; as an illustration, we combine electrostatic doping and low work function contact engineering to achieve CNFET CMOS with symmetric NMOS and PMOS ( i.e., CNFET ON-current for NMOS and PMOS is within 6% of each other). Thus, this work realizes a solid-state, air-table, very large scale integration and silicon CMOS compatible doping strategy, enabling integration of CNFET CMOS within standard fabrication processes today.

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip.

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Carbon nanotube computer.

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

Linear increases in carbon nanotube density through multiple transfer technique.

We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. We perform multiple transfers, whereby we transfer CNTs from several growth wafers onto the same target surface, thereby linearly increasing CNT density on the target substrate. This process, called transfer of nanotubes through multiple sacrificial layers, is highly scalable, and we demonstrate linear CNT density scaling up to 5 transfers. We also demonstrate that this linear CNT density increase results in an ideal linear increase in drain-source currents of carbon nanotube field effect transistors (CNFETs). Experimental results demonstrate that CNT density can be improved from 2 to 8 CNTs/µm, accompanied by an increase in drain-source CNFET current from 4.3 to 17.4 µA/µm.