Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate.

In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors's knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.

Interlayer exchange couple based reliable and robust 3-input adder design methodology.

In this paper, a novel inter-layer exchange coupled (IEC) based 3-input full adder design methodology is proposed and subsequently the architecture has been implemented on the widely accepted micromagnetic OOMMF platform. The impact of temperature on the IEC coupled full-adder design has been analyzed up to Curie temperature. It was observed that even up to Curie temperature the IEC based adder design was able to operate at sub-50 nm as contrast to dipole coupled adder design which failed at 5 K for sub 50 nm. Simulation results obtained from OOMMF micromagnetic simulator shows, the IEC based adder design was at a lower energy state as compared to the dipole coupled adder indicating a more stable system and as the temperature of the design was increased, the total energy increased resulting in reduced stability. Potential explanation for the thermodynamic stability of IEC model lies in its energetically favored architecture, such that the total energy was lower than its dipole coupled counterparts. IEC architecture demonstrates supremacy in reliability and strength enabling NML to march towards beyond CMOS devices.

A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design.

In this paper, we propose an interlayer exchange coupling (IEC) based 3D universal NAND/NOR gate design methodology for the reliable and robust implementation of nanomagnetic logic design as compared to the state-of-the art architectures. Owing to stronger coupling scheme as compared to the conventional dipole coupling, the random flip of the states of the nanomagnets (i.e. the soft error) is reduced resulting in greater scalability and better data retention at the deep sub-micron level. Results obtained from Object Oriented Micromagnetic Framework micromagnetic simulation show even at a Curie temperature of the nanomagnets coupled through IEC, the logic function works properly as opposed to dipole coupled nanomagnets which fails at 5 K when scaled down to sub 50 nm. Contemplating the fabrication challenges, the robustness of the IEC design was studied for structural defects, positional misalignment, shape, and size variations. This proposed 3D universal gate design methodology benefits from the miniaturization of nanomagnets as well as reduces the effect of thermally induced errors resulting in opening up a new perspective for nanomagnet based design in magneto-logic devices.

Temperature and Size Effect on the Electrical Properties of Monolayer Graphene based Interconnects for Next Generation MQCA based Nanoelectronics.

Graphene interconnects have been projected to out-perform Copper interconnects in the next generation Magnetic Quantum-dot Cellular Automata (MQCA) based nano-electronic applications. In this paper a simple two-step lithography process for patterning CVD monolayer graphene on SiO2/Si substrate has been used that resulted in the current density of one order higher magnitude as compared to the state-of-the-art graphene-based interconnects. Electrical performances of the fabricated graphene interconnects were evaluated, and the impact of temperature and size on the current density and reliability was investigated. The maximum current density of 1.18 ×108 A/cm2 was observed for 0.3 µm graphene interconnect on SiO2/Si substrate, which is about two orders and one order higher than that of conventionally used copper interconnects and CVD grown graphene respectively, thus demonstrating huge potential in outperforming copper wires for on-chip clocking. The drop in current at 473 K as compared to room temperature was found to be nearly 30%, indicating a positive temperature coefficient of resistivity (TCR). TCR for all cases were studied and it was found that with decrease in width, the sensitivity of temperature also reduces. The effect of resistivity on the breakdown current density was analysed on the experimental data using Matlab and found to follow the power-law equations. The breakdown current density was found to have a reciprocal relationship to graphene interconnect resistivity suggesting Joule heating as the likely mechanism of breakdown.

Nanomagnetic logic based runtime Reconfigurable area efficient and high speed adder design methodology.

In this study, we present a runtime reconfigurable nanomagnetic (RRN) adder design offering significant area efficiency and high speed operations. Subsequently, it is implemented using a micromagnetic simulation tool, by exploiting the reversal magnetization and energy minimization nature of the nanomagnets. We compute the carry and sum of the 1-bit full adder using only two majority gates comprising a total of 7 nanomagnets and single design layout. Consequently, the on-chip clocking schematic for the proposed RRN adder implementation for both horizontal and vertical layouts are introduced. The quantitative analysis of the required resources for higher bit adder architecture using the proposed design is performed and compared with state-of-the art. The proposed design methodology leads to ∼86%, ∼83% and ∼93% reduction in the number of nanomagnets, majority gates and clock cycles respectively resulting in an area efficient and high speed RRN adder architecture.

Dipole coupled magnetic quantum-dot cellular automata-based efficient approximate nanomagnetic subtractor and adder design approach.

In this paper, we propose a dipole coupled magnetic quantum-dot cellular automata-based approximate nanomagnetic (APN) architectural design approach for subtractor and adder. In addition, we also introduce an APN architecture which offers runtime reconfigurability using a single design layout comprising only four nanomagnets. Subsequently, we propose the APN add/sub architecture by exploiting shape anisotropy and ferromagnetically coupled fixed input majority gate. The proposed APN architecture designs have been implemented using a micromagnetic simulation tool and performance has been compared with the state-of-the-art approach resulting in a ∼50%-80% reduction in the number of nanomagnets and clock cycles without degradation in the accuracy leading to area and energy efficiency.

Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate.

In this letter, we introduce the magnetic quantum-dot cellular automata (MQCA) based area and speed efficient design approach for nanomagnetic full adder implementation. We exploited the physical properties of three input MQCA majority gate (MG), where the fixed input of the MG is coupled ferromagnetically to one of the primary input operands. Subsequently we propose a design methodology, mapping logic and micromagnetic software implementation, validation of the binary full adder architecture built using two-three inputs MQCA MGs. In addition, we also analyzed our proposed design for switching errors to ensure bit stability and reliability. Our proposed design leads to ∼36%-69% reduction in the number of nanomagnets, ∼50%-75% reduction in the number of clock cycles and ∼33%-50% reduction in the number of MG operations required for the binary full adder implementation compared to the state of art designs.

Tunable intrinsic magnetic phase transition in pristine single-layer graphene nanoribbons.

In this paper, we report on the interesting phenomenon of magnetic phase transitions (MPTs) observed under the combined influence of an electric field (E) and temperature (T) leading to a thermo-electromagnetic effect on the pristine single-layer zigzag graphene nanoribbon (szGNR). Density functional theory-based first principles calculations have been deployed for this study on the intrinsic magnetic properties of graphene. Interestingly, by tuning electric field (E) and temperature (T), three distinct magnetic phase behaviors, para-, ferro- and antiferromagnetic are exhibited in pristine szGNR. We have investigated the unrivaled positional parameters of these MPTs. MPT occurring in the system also follows a positional trend and the change in these positional parameters with regard to the size of the szGNR along with the varied E and T is studied. We propose a bow-tie schematic to induce the intrinsic magnetism in graphene and present the envisaged model of the processor application with the reported intrinsic MPT in szGNR. This fundamental insight into the intrinsic MPTs in graphene is an essential step towards developing graphene-based spin-transfer torque magnetoresistive random access memory, quantum computing devices, magnonics and spintronic memory application.