Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method.

In this work, electrical characteristics of L-shaped tunneling field-effect transistors (TFETs) have been studied and optimized by a commercial device simulator: Synopsys Sentaurus. Unlike our previous study performed by using Silvaco Atlas, there exists a kink phenomenon in a transfer curve which degrades the subthreshold swing (SS) and on-current (lon) of TFETs. According to simulation results, the kink results from abrupt source doping. Rounding the source junction edge with gradual doping profile is helpful to alleviate it. Based on those results, a novel fabrication flow has been proposed to suppress the kink effect induced by source corners. It is predicted that the performance of L-shaped TFETs is improved in terms of SS and Ion under the optimized process condition. Furthremore, the effect of high-k gate dielectric and narrow band gap material on device performance has been examined. Using 2-nm-thick HfO2 for gate dielectric and Si0.7Ge0.3 for intrinsic tunneling region, gate controllability to the channel and tunneling probability have been enhanced. As a result, its threshold voltage (Vth), SS and Ion have been improved by 0.13 V, 16 mV/dec, and 3.62 microA/microm, respectively.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

A novel fabrication method for the nanoscale tunneling field effect transistor.

Tunneling Field Effect Transistors (TFETs) are considered as a candidate for low power applications. However, most of TFETs have been researched on only for long channels due to the misalignment problem that occurs during the source/drain doping process in device fabrication. Thus, a new method is proposed for the fabrication of TFETs in nanoscale regions. This proposed fabrication process does not need an additional mask to define the source/drain regions, and makes it possible to form a self-aligned source/drain doping process. In addition, through TCAD simulation, the electrical characteristics of a TFET with dopant engineering and a rounded gate edge shape for a higher on/off current ratio were investigated. As a result, the TFET showed the properties of a larger on-current, a lower average subthreshold swing (58.5 mV/dec), and a 30-fold smaller leakage current compared to the conventional TFET The TFET with dopant engineering and a rounded gate edge shape can also be fabricated simply through the proposed fabrication process.

Split-gate-structure 1T DRAM for retention characteristic improvement.

As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical issues in its commercialization. In the selection of a bias condition for 1T DRAM, however, it is impossible to choose a gate bias condition that is suitable for both the "1" and "0" hold state data. In this paper, a split gate structure and hold bias scheme are proposed for the simultaneous improvement of the "1" and "0" data retention characteristics. It was confirmed through numerical simulation that this structure has a more than 3 sec retention time. A vertical gate-all-around split-gate structure and its fabrication method are also suggested to achieve high density, low cost, a higher sensing margin, and a longer retention time.