RESUMEN
A retention behavior model for self-rectifying TaO/HfO x - and TaO/AlO x -based resistive random-access memory (RRAM) is proposed. Trapping-type RRAM can have a high resistance state (HRS) and a low resistance state (LRS); the degradation in a LRS is usually more severe than that in a HRS, because the LRS during the SET process is limited by the internal resistor layer. However, if TaO/AlO x elements are stacked in layers, the LRS retention can be improved. The LRS retention time estimated by extrapolation method is more than 5 years at room temperature. Both TaO/HfO x - and TaO/AlO x -based RRAM structures have the same capping layer of TaO, and the activation energy levels of both types of structures are 0.38 eV. Moreover, the additional AlO x switching layer of a TaO/AlO x structure creates a higher O diffusion barrier that can substantially enhance retention, and the TaO/AlO x structure also shows a quite stable LRS under biased conditions.
RESUMEN
Ti/HfOx-based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, detailed understanding about the nature of Ti thickness-dependent asymmetric switching is still missing. To realize this, the present work addresses the effects of Ti buffer layer thickness on the switching properties of TiN/Ti/HfOx/TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of the Ti layer on the HfOx dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R-BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during the first RESET operation by decreasing the FORMING voltage. Furthermore, the memory device shows good nonvolatility at â¼1 µA programming current by selecting a proper thickness of Ti buffer layer. To achieve reliable BRS properties for low power application, the operation current has been further optimized, whereas the memory device shows pulse endurance of more than 7 million cycles at a low pulse width of 50 ns and excellent data retention properties of more than 40 h at 150 °C measurement temperature.
