Measurement of Thermal Stress by X-ray Nano-Diffraction in (111)-Oriented Nanotwinned Cu Bumps for Cu/SiO2 Hybrid Joints.

X-ray nanodiffraction was used to measure the thermal stress of 10 µm nanotwinned Cu bumps in Cu/SiO2 hybrid structures at -55 °C, 27 °C, 100 °C, 150 °C, and 200 °C. Bonding can be achieved without externally applied compression. The X-ray beam size is about 100 nm in diameter. The Cu bump is dominated by (111) oriented nano-twins. Before the hybrid bonding, the thermal stress in Cu bumps is compressive and remains compressive after bonding. The average stress in the bonded Cu joint at 200 °C is as large as -169.1 MPa. In addition, using the strain data measured at various temperatures, one can calculate the effective thermal expansion coefficient (CTE) for the 10 µm Cu bumps confined by the SiO2 dielectrics. This study reports a useful approach on measuring the strain and stress in oriented metal bumps confined by SiO2 dielectrics. The results also provide a deeper understanding on the mechanism of hybrid bonding without externally applied compression.

Twin-Boundary Reduced Surface Diffusion on Electrically Stressed Copper Nanowires.

Surface diffusion is intimately correlated with crystal orientation and surface structure. Fast surface diffusion accelerates phase transformation and structural evolution of materials. Here, through in situ transmission electron microscopy observation, we show that a copper nanowire with dense nanoscale coherent twin-boundary (CTB) defects evolves into a zigzag configuration under electric-current driven surface diffusion. The hindrance at the CTB-intercepted concave triple junctions decreases the effective surface diffusivity by almost 1 order of magnitude. The energy barriers for atomic migration at the concave junctions and different faceted surfaces are computed using density functional theory. We proposed that such a stable zigzag surface is shaped not only by the high-diffusivity facets but also by the stalled atomic diffusion at the concave junctions. This finding provides a defect-engineering route to develop robust interconnect materials against electromigration-induced failures for nanoelectronic devices.

Uphill Diffusion Induced Point Contact Reaction in Si Nanowires.

The events of repeating nucleation in point contact reactions between nanowires of Si and Ni or Co have been revisited here due to uphill diffusion as well as an extremely high supersaturation, over a factor of 1000, needed for the nucleation. Also what is the diameter of the point contact needs to be defined. The stepwise growth of nanoscale epitaxial silicide can occur because the repeating nucleation events are restricted in nanoscale wires.

Artificial intelligence deep learning for 3D IC reliability prediction.

Three-dimensional integrated circuit (3D IC) technologies have been receiving much attention recently due to the near-ending of Moore's law of minimization in 2D IC. However, the reliability of 3D IC, which is greatly influenced by voids and failure in interconnects during the fabrication processes, typically requires slow testing and relies on human's judgement. Thus, the growing demand for 3D IC has generated considerable attention on the importance of reliability analysis and failure prediction. This research conducts 3D X-ray tomographic images combining with AI deep learning based on a convolutional neural network (CNN) for non-destructive analysis of solder interconnects. By training the AI machine using a reliable database of collected images, the AI can quickly detect and predict the interconnect operational faults of solder joints with an accuracy of up to 89.9% based on non-destructive 3D X-ray tomographic images. The important features which determine the "Good" or "Failure" condition for a reflowed microbump, such as area loss percentage at the middle cross-section, are also revealed.

Low-Temperature Cu/SiO2 Hybrid Bonding with Low Contact Resistance Using (111)-Oriented Cu Surfaces.

We adopted (111)-oriented Cu with high surface diffusivity to achieve low-temperature and low-pressure Cu/SiO2 hybrid bonding. Electroplating was employed to fabricate arrays of Cu vias with 78% (111) surface grains. The bonding temperature can be lowered to 200 °C, and the pressure is as low as 1.06 MPa. The bonding process can be accomplished by a 12-inch wafer-to-wafer scheme. The measured specific contact resistance is 1.2 × 10-9 Ω·cm2, which is the lowest value reported in related literature for Cu-Cu joints bonded below 300 °C. The joints possess excellent thermal stability up to 375 °C. The bonding mechanism is also presented to provide more understanding on hybrid bonding.

Tensile Properties and Thermal Stability of Unidirectionally <111>-Oriented Nanotwinned and <110>-Oriented Microtwinned Copper.

Tensile tests on two kinds of electroplated copper foils with twins before and after annealing were performed. One electroplating parameter results in a microstructure of <110>-oriented microtwinned Cu (mt-Cu), and the other is <111>-oriented nanotwinned Cu (nt-Cu). The latter shows higher thermal stability than the former after annealing. Though the toughness for the two as-plated foils are quite close, the toughness for the <111> oriented nt-Cu increased from 34 to 74 MJ/m3 after annealing at 250 °C for 3 h. In comparison, the toughness of the <110>-oriented mt-Cu remained almost the same after annealing.

Tensile Properties of <111>-Oriented Nanotwinned Cu with Different Columnar Grain Structures.

We performed tensile tests on highly <111>-oriented nanotwinned copper (nt-Cu) foils with different columnar grain structures. For a systematic study, we altered the microstructure of the foils by tuning the electroplating electrolyte and annealing temperatures under a nitrogen atmosphere. The results show that the yield strength ranges from 300 to 700 MPa, and elongation spans from 5% to 25%. Knowing the measured twin spacing and average grain size, and combining the confined layer slip with the Hall-Petch equation, we calculated the theoretical yield strength of the nt-Cu with different microstructures, and the theoretic values match the experiment results. Owing to the unique crystal orientation properties of <111>-oriented columnar grains, dislocations induced by slip are very limited. The Schmid factor of grains along the tensile axis direction is highly identical, so the plastic deformation is much more suitably explained by the Schmid factor model. Thus, we replace the Taylor factor with the Schmid factor in the slip model of nt-Cu.

Electromigration Mechanism of Failure in Flip-Chip Solder Joints Based on Discrete Void Formation.

In this investigation, SnAgCu and SN100C solders were electromigration (EM) tested, and the 3D laminography imaging technique was employed for in-situ observation of the microstructure evolution during testing. We found that discrete voids nucleate, grow and coalesce along the intermetallic compound/solder interface during EM testing. A systematic analysis yields quantitative information on the number, volume, and growth rate of voids, and the EM parameter of DZ*. We observe that fast intrinsic diffusion in SnAgCu solder causes void growth and coalescence, while in the SN100C solder this coalescence was not significant. To deduce the current density distribution, finite-element models were constructed on the basis of the laminography images. The discrete voids do not change the global current density distribution, but they induce the local current crowding around the voids: this local current crowding enhances the lateral void growth and coalescence. The correlation between the current density and the probability of void formation indicates that a threshold current density exists for the activation of void formation. There is a significant increase in the probability of void formation when the current density exceeds half of the maximum value.

Intermetallic compounds in 3D integrated circuits technology: a brief review.

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Approaching the ideal elastic strain limit in silicon nanowires.

Achieving high elasticity for silicon (Si) nanowires, one of the most important and versatile building blocks in nanoelectronics, would enable their application in flexible electronics and bio-nano interfaces. We show that vapor-liquid-solid-grown single-crystalline Si nanowires with diameters of ~100 nm can be repeatedly stretched above 10% elastic strain at room temperature, approaching the theoretical elastic limit of silicon (17 to 20%). A few samples even reached ~16% tensile strain, with estimated fracture stress up to ~20 GPa. The deformations were fully reversible and hysteresis-free under loading-unloading tests with varied strain rates, and the failures still occurred in brittle fracture, with no visible sign of plasticity. The ability to achieve this "deep ultra-strength" for Si nanowires can be attributed mainly to their pristine, defect-scarce, nanosized single-crystalline structure and atomically smooth surfaces. This result indicates that semiconductor nanowires could have ultra-large elasticity with tunable band structures for promising "elastic strain engineering" applications.

Optimization of the nanotwin-induced zigzag surface of copper by electromigration.

By adding nanotwins to Cu, the surface electromigration (EM) slows down. The atomic mobility of the surface step-edges is retarded by the triple points where a twin meets a free surface to form a zigzag-type surface. We observed that EM can alter the zigzag surface structure to optimize the reduction of EM, according to Le Chatelier's principle. Statistically, the optimal alternation is to change an arbitrary (111)/(hkl) zigzag pair to a pair having a very low index (hkl) plane, especially the (200) plane. Using in situ ultrahigh vacuum and high-resolution transmission electron microscopy, we examined the effects of different zigzag surfaces on the rate of EM. The calculated rate of surface EM can be decreased by a factor of ten.

Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu.

Direct Cu-to-Cu bonding was achieved at temperatures of 150-250 °C using a compressive stress of 100 psi (0.69 MPa) held for 10-60 min at 10(-3) torr. The key controlling parameter for direct bonding is rapid surface diffusion on (111) surface of Cu. Instead of using (111) oriented single crystal of Cu, oriented (111) texture of extremely high degree, exceeding 90%, was fabricated using the oriented nano-twin Cu. The bonded interface between two (111) surfaces forms a twist-type grain boundary. If the grain boundary has a low angle, it has a hexagonal network of screw dislocations. Such network image was obtained by plan-view transmission electron microscopy. A simple kinetic model of surface creep is presented; and the calculated and measured time of bonding is in reasonable agreement.

Nanoscale Joule heating and electromigration enhanced ripening of silver nanowire contacts.

Solution-processed metallic nanowire thin film is a promising candidate to replace traditional indium tin oxide as the next-generation transparent and flexible electrode. To date however, the performance of these electrodes is limited by the high contact resistance between contacting nanowires; so improving the point contacts between these nanowires remains a major challenge. Existing methods for reducing the contact resistance require either a high processing power, long treatment time, or the addition of chemical reagents, which could lead to increased manufacturing cost and damage the underlying substrate or device. Here, a nanoscale point reaction process is introduced as a fast and low-power-consumption way to improve the electrical contact properties between metallic nanowires. This is achieved via current-assisted localized joule heating accompanied by electromigration. Localized joule heating effectively targets the high-resistance contact points between nanowires, leading to the automatic removal of surface ligands, welding of contacting nanowires, and the reshaping of the contact pathway between the nanowires to form a more desirable geometry of low resistance for interwire conduction. This result shows the interplay between thermal and electrical interactions at the highly reactive nanocontacts and highlights the control of the nanoscale reaction as a simple and effective way of turning individual metallic nanowires into a highly conductive interconnected nanowire network. The temperature of the adjacent device layers can be kept close to room temperature during the process, making this method especially suitable for use in devices containing thermally sensitive materials such as polymer solar cells.

Nucleation and atomic layer reaction in nickel silicide for defect-engineered Si nanochannels.

At the nanoscale, defects can significantly impact phase transformation processes and change materials properties. The material nickel silicide has been the industry standard electrical contact of silicon microelectronics for decades and is a rich platform for scientific innovation at the conjunction of materials and electronics. Its formation in nanoscale silicon devices that employ high levels of strain, intentional, and unintentional twins or grain boundaries can be dramatically different from the commonly conceived bulk processes. Here, using in situ high-resolution transmission electron microscopy (HRTEM), we capture single events during heterogeneous nucleation and atomic layer reaction of nickel silicide at various crystalline boundaries in Si nanochannels for the first time. We show through systematic experiments and analytical modeling that unlike other typical face-centered cubic materials such as copper or silicon the twin defects in NiSi2 have high interfacial energies. We observe that these twin defects dramatically change the behavior of new phase nucleation and can have direct implications for ultrascaled devices that are prone to defects or may utilize them to improve device performance.

Direct measurement of coherency limits for strain relaxation in heteroepitaxial core/shell nanowires.

The growth of heteroepitaxially strained semiconductors at the nanoscale enables tailoring of material properties for enhanced device performance. For core/shell nanowires (NWs), theoretical predictions of the coherency limits and the implications they carry remain uncertain without proper identification of the mechanisms by which strains relax. We present here for the Ge/Si core/shell NW system the first experimental measurement of critical shell thickness for strain relaxation in a semiconductor NW heterostructure and the identification of the relaxation mechanisms. Axial and tangential strain relief is initiated by the formation of periodic a/2 <110> perfect dislocations via nucleation and glide on {111} slip-planes. Glide of dislocation segments is directly confirmed by real-time in situ transmission electron microscope observations and by dislocation dynamics simulations. Further shell growth leads to roughening and grain formation which provides additional strain relief. As a consequence of core/shell strain sharing in NWs, a 16 nm radius Ge NW with a 3 nm Si shell is shown to accommodate 3% coherent strain at equilibrium, a factor of 3 increase over the 1 nm equilibrium critical thickness for planar Si/Ge heteroepitaxial growth.

Ultrashort channel silicon nanowire transistors with nickel silicide source/drain contacts.

We demonstrate the shortest transistor channel length (17 nm) fabricated on a vapor-liquid-solid (VLS) grown silicon nanowire (NW) by a controlled reaction with Ni leads on an in situ transmission electron microscope (TEM) heating stage at a moderate temperature of 400 °C. NiSi(2) is the leading phase, and the silicide-silicon interface is an atomically sharp type-A interface. At such channel lengths, high maximum on-currents of 890 (µA/µm) and a maximum transconductance of 430 (µS/µm) were obtained, which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in a large number of SB-FETs with channel lengths in the range of 17 nm to 3.6 µm. Our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, which is different from that in conventional MOSFETs, and that limits transport parameter extraction from SB-FETs using conventional field-effect transconductance measurements.

Study of Ni Metallization in Macroporous Si Using Wet Chemistry for Radio Frequency Cross-Talk Isolation in Mixed Signal Integrated Circuits.

A highly conductive moat or Faraday cage of through-the-wafer thickness in Si substrate was proposed to be effective in shielding electromagnetic interference thereby reducing radio frequency (RF) cross-talk in high performance mixed signal integrated circuits. Such a structure was realized by metallization of selected ultra-high-aspect-ratio macroporous regions that were electrochemically etched in p- Si substrates. The metallization process was conducted by means of wet chemistry in an alkaline aqueous solution containing Ni2+ without reducing agent. It is found that at elevated temperature during immersion, Ni2+ was rapidly reduced and deposited into macroporous Si and a conformal metallization of the macropore sidewalls was obtained in a way that the entire porous Si framework was converted to Ni. A conductive moat was as a result incorporated into p- Si substrate. The experimentally measured reduction of crosstalk in this structure is 5~18 dB at frequencies up to 35 GHz.

Inhibiting Adatom diffusion through surface alloying.

Ab initio and kinetic Monte Carlo calculations elucidate the electronic nature of surface Sn alloying on the stability and mobility of a Cu adatom on the Cu-Sn (111) alloy surface. Sn atoms segregate on the surface and introduce forbidden areas around them within which adatom adsorption is strictly prohibited. In addition they reduce dramatically both the binding and the mobility of Cu adatoms in neighboring adsorption sites outside the forbidden areas, in contrast to experimental suggestions. Thus, Sn atoms act as blocking sites inhibiting the Cu adatom diffusion. The underlying mechanisms are the structural deformation associated with the oversized Sn atoms and the enhancement of the adatom-surface interaction in the vicinity of Sn atoms.

Homogeneous nucleation of epitaxial CoSi2 and NiSi in Si nanowires.

Homogeneous nucleation is rare except in theory. We observed repeating events of homogeneous nucleation in epitaxial growth of CoSi(2) and NiSi silicides in nanowires of silicon by using high resolution TEM. The growth of every single atomic layer requires nucleation. Heterogeneous nucleation is prevented because of non-microreversibility between the oxide/Si and oxide/silicide interfaces. We determined the incubation time of homogeneous nucleation. The calculated and the measured nucleation rates are in good agreement. We used Zeldovich factor to estimate the number of molecules in the critical nucleus; it is about 10 and reasonable. A very high supersaturation is found for the homogeneous nucleation.

Preparation of hierarchically porous nickel from macroporous silicon.

A novel approach for preparing hierarchical porous nickel structures has been developed. It is an aqueous processing of the template, macroporous silicon, which was etched in HF solution to have straight channels. By immersion in a prepared nickel solution, the silicon sidewalls were replaced by nickel deposits to form a total metallic structure. Since silicon framework was gradually consumed during the displacement reactions, the deposited nickel displayed additional feature of being highly porous on the sidewalls. With the initial straight microchannels, the metal structure was hierarchically porous.