Hardware implementation of memristor-based artificial neural networks.

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

Hybrid 2D-CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2-Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D-CMOS hybrid microchips for memristive applications-CMOS stands for complementary metal-oxide-semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

Standards for the Characterization of Endurance in Resistive Switching Devices.

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

Graphene-Boron Nitride-Graphene Cross-Point Memristors with Three Stable Resistive States.

Two-dimensional (2D) material-based memristors have shown several properties that are not shown by traditional ones, such as high transparency, robust mechanical strength and flexibility, superb chemical stability, enhanced thermal heat dissipation, ultralow power consumption, coexistence of bipolar and threshold resistive switching, and ultrastable relaxation when used as electronic synapse (among others). However, several electrical performances often required in memristive applications, such as the generation of multiple stable resistive states for high-density information storage, still have never been demonstrated. Here, we present the first 2D material-based memristors that exhibit three stable and well-distinguishable resistive states. By using a multilayer hexagonal boron nitride (h-BN) stack sandwiched by multilayer graphene (G) electrodes, we fabricate 5 µm × 5 µm cross-point Au/Ti/G/h-BN/G/Au memristors that can switch between each two or three resistive states, depending on the current limitation (CL) and reset voltage used. The use of graphene electrodes plus a small cross-point structure are key elements to observe the tristate operation, which has not been observed in larger (100 µm × 100 µm) devices with an identical Au/Ti/G/h-BN/G/Au structure nor in similar small (5 µm × 5 µm) devices without graphene interfacial layers (i.e., Au/Ti/h-BN/Au). Basically, we generate an intermediate state between the high resistive state and the low resistive state (LRS), named soft-LRS (S-LRS), which may be related to the formation of a narrower conductive nanofilament across the h-BN because of the ability of graphene to limit metal penetration (at low CLs). All the 2D materials have been fabricated using the scalable chemical vapor deposition approach, which is an immediate advantage compared to other works using mechanical exfoliated 2D materials.

Electrical Homogeneity of Large-Area Chemical Vapor Deposited Multilayer Hexagonal Boron Nitride Sheets.

Large-area hexagonal boron nitride (h-BN) can be grown on polycrystalline metallic substrates via chemical vapor deposition (CVD), but the impact of local inhomogeneities on the electrical properties of the h-BN and their effect in electronic devices is unknown. Conductive atomic force microscopy (CAFM) and probe station characterization show that the tunneling current across the h-BN stack fluctuates up to 3 orders of magnitude from one substrate (Pt) grain to another. Interestingly, the variability in the tunneling current across the h-BN within the same substrate grain is very low, which may enable the use of CVD-grown h-BN in ultra scaled technologies.

Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride.

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.