Characteristics of Carbon Nanotube Cold Cathode Triode Electron Gun Driven by MOSFET Working at Subthreshold Region.

The carbon nanotube cold cathode has important applications in the X-ray source, microwave tube, neutralizer, etc. In this study, the characteristics of carbon nanotube (CNT) electron gun in series with metal-oxide-semiconductor field-effect transistor (MOSFET) were studied. CNTs were prepared on a stainless steel substrate by chemical vapor deposition and assembled with a mesh gate to form an electron gun. The anode current of the electron gun can be accurately regulated by precisely controlling the MOSFET gate voltage in the subthreshold region from 1 to 40 µA. The current stability measurements show the cathode current fluctuation was 0.87% under 10 h continuous operation, and the corresponding anode current fluctuation was 2.3%. The result has demonstrated that the MOSFET can be applied for the precise control of the CNT electron gun and greatly improve current stability.

Switching and Frequency Response Assessment of Photovoltaic Drivers and Their Potential for Different Applications.

Newly introduced Photovoltaic (PV) devices, featuring a built-in chip with an illuminating Light Emitting Diode (LED), have emerged in the commercial market. These devices are touted for their utility as both low- and high-side power switch drivers and for data acquisition coupling. However, comprehensive knowledge and experimentation regarding the limitations of these Photovoltaic Drivers in both switching and signal processing applications remain underexplored. This paper presents a detailed characterization of a Photovoltaic Driver, focusing on its performance under resistive and capacitive loads. Additionally, it delineates the device's constraints when employed in signal processing. Through the analysis of switching losses across various power switches (Silicon and Silicon Carbide) in both series and parallel driver configurations, this study assesses the driver's efficacy in operating Junction Field-Effect Transistors (JFETs). Findings suggest that Photovoltaic Drivers offer a low-cost, compact solution for specific applications, such as high-voltage, low-bandwidth measurements, and low-speed turn-on with fast turn-off power switching scenarios, including solid-state switches and hot-swap circuits. Moreover, they present a straightforward, cost-effective method for driving JFETs, simplifying the circuit design and eliminating the need for an additional negative power source.

A Novel 4H-SiC SGT MOSFET with Improved P+ Shielding Region and Integrated Schottky Barrier Diode.

A silicon carbide (SiC) SGT MOSFET featuring a ""-shaped P+ shielding region (PSR), named SPDT-MOS, is proposed in this article. The improved PSR is introduced as a replacement for the source trench to enhance the forward performance of the device. Its improvement consists of two parts. One is to optimize the electric field distribution of the device, and the other is to expand the current conduction path. Based on the improved PSR and grounded split gate (SG), the device remarkably improves the conduction characteristics, gate oxide reliability, and frequency response. Moreover, the integrated sidewall Schottky barrier diode (SBD) prevents the inherent body diode from being activated and improves the reverse recovery characteristics. As a result, the gate-drain capacitance, gate charge, and reverse recovery charge (Qrr) of the SPDT-MOS are 81.2%, 41.2%, and 90.71% lower than those of the DTMOS, respectively. Compared to the double shielding (DS-MOS), the SPDT-MOS exhibits a 20% reduction in on-resistance and an 8.1% increase in breakdown voltage.

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function.

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al. Device figure of merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/µm, has been achieved by tuning the channel doping concentration (ND) to 1 × 1019 cm-3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24 × 10-16 A/µm and power dissipation of 9.69 × 10-17 W/µm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56 × 1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.

A Novel 4H-SiC Asymmetric MOSFET with Step Trench.

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (Cgd) to the gate-to-source capacitance (Cgs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (Ron,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (RJFET) and the electric field in the gate oxide (Eox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design.

A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures.

This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical-thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters' degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability.

Sensitive Detection of Oral Leukoplakia: Analyzing P90 Biomarkers in Saliva and Tissue.

Oral cancer represents a significant global public health challenge, contributing substantially to the incidence and mortality of cancer. Despite established risk factors such as tobacco use and alcohol consumption, early detection remains crucial for effective treatment. This study introduces a novel approach using a transistor-based biosensor system for detecting the P90 (CIP2A) protein. We tested the presence of CIP2A in human leukoplakia samples, which can undergo malignant conversion into aggressive oral squamous cell carcinoma. The method used commercially available glucose test strips functionalized with P90 antibodies, providing high sensitivity and a low limit of detection which was five orders lower than that of commercial ELISA kits. A specially designed printed circuit board (PCB) facilitated accurate measurements, and the device's performance was optimized through characteristic tests. Human sample testing validated the biosensor's effectiveness in distinguishing samples after cell lysis. This study contributes to advancing accurate and cost-effective diagnostic approaches for oral pre-cancer and cancer tissues.

Research on Single-Event Burnout Reinforcement Structure of SiC MOSFET.

In this paper, the single-event burnout (SEB) and reinforcement structure of 1200 V SiC MOSFET (SG-SBD-MOSFET) with split gate and Schottky barrier diode (SBD) embedded were studied. The device structure was established using Sentaurus TCAD, and the transient current changes of single-event effect (SEE), SEB threshold voltage, as well as the regularity of electric field peak distribution transfer were studied when heavy ions were incident from different regions of the device. Based on SEE analysis of the new structural device, two reinforcement structure designs for SEB resistance were studied, namely the expansion of the P+ body contact area and the design of a multi-layer N-type interval buffer layer. Firstly, two reinforcement schemes for SEB were analyzed separately, and then comprehensive design and analysis were carried out. The results showed that the SEB threshold voltage of heavy ions incident from the N+ source region was increased by 16% when using the P+ body contact area extension alone; when the device is reinforced with a multi-layer N-type interval buffer layer alone, the SEB threshold voltage increases by 29%; the comprehensive use of the P+ body contact area expansion and a multi-layer N-type interval buffer layer reinforcement increased the SEB threshold voltage by 33%. Overall, the breakdown voltage of the reinforced device decreased from 1632.935 V to 1403.135 V, which can be seen as reducing the remaining redundant voltage to 17%. The device's performance was not significantly affected.

A comprehensive Study of the Out of Field Non Target Dose Associated with 6 and 10 MV Flattened and Flattening Filter Free X Ray Beam in a True Beam Linear Accelerator.

AIM: To evaluate the out-of-field dose associated with flattened (FF) and flattening filter-free (FFF) 6 and 10 MV X-ray beams in a TrueBeam linear accelerator (Linac). MATERIALS AND METHODS: Measurements were taken in a slab phantom using the metal oxide semiconductor field effect transistor (MOSFET) detector at varying depths (dmax, 5 cm, and 10 cm) for clinically relevant field sizes and up to 30 cm from the field edges for 6 and 10 MV FF and FFF beams in TrueBeam Linac. Dose calculation accuracy of the analytic anisotropic algorithm (AAA) and Acuros algorithm was investigated in the out-of-field region. Similarly, the out-of-field dose associated with volumetric modulated arc therapy (VMAT) head-and-neck plan delivered to a body phantom was evaluated. RESULTS: The out-of-field dose for both FF and FFF photon beams (6 and 10 MV) decreased with increasing distance from the field boundary and size. Furthermore, regardless of FF in the field, higher-energy photon beams were associated with lower out-of-field dose. Both algorithms underestimated the dose in the out-of-field region, with AAA failing to calculate the out-of-field dose at 15 cm from the field edge and Acuros failing to calculate out-of-field radiation at 20 cm. At 5 cm from the field edge, an average of 50% underestimation was observed, and at 10 cm, an average of 60% underestimation was observed for both FF and FFF (6 and 10 MV) beams. The VMAT head-and-neck plan performed with the FFF beam resulted in a lower out-of-field dose than the FF beam for a comparable dose distribution. CONCLUSION: Compared with flattened beams, the FFF modes on TrueBeam Linac exhibited a clinically relevant reduction in the out-of-field dose. Further dosimetric studies are warranted to determine the significant benefit of FFF beams across different cancer sites.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope ß. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

A Novel Asymmetric Trench SiC Metal-Oxide-Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance.

In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics. The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (Vcut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Qgd). Through TCAD simulation, the HJD-ATMOS decreases Vcut-in by 53.04% compared to the C-ATMOS. Both Qgd and switching loss are reduced, with a decrease of 31.91% in Qgd and 40.29% in switching loss.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

An Investigation of Body Diode Reliability in Commercial 1.2 kV SiC Power MOSFETs with Planar and Trench Structures.

The body diode degradation in SiC power MOSFETs has been demonstrated to be caused by basal plane dislocation (BPD)-induced stacking faults (SFs) in the drift region. To enhance the reliability of the body diode, many process and structural improvements have been proposed to eliminate BPDs in the drift region, ensuring that commercial SiC wafers for 1.2 kV devices are of high quality. Thus, investigating the body diode reliability in commercial planar and trench SiC power MOSFETs made from SiC wafers with similar quality has attracted attention in the industry. In this work, current stress is applied on the body diodes of 1.2 kV commercial planar and trench SiC power MOSFETs under the off-state. The results show that the body diodes of planar and trench devices with a shallow P+ depth are highly reliable, while those of the trench devices with the deep P+ implantation exhibit significant degradation. In conclusion, the body diode degradation in trench devices is mainly influenced by P+ implantation-induced BPDs. Therefore, a trade-off design by controlling the implantation depth/dose and maximizing the device performance is crucial. Moreover, the deep JFET design is confirmed to further improve the body diode reliability in planar devices.

RC-Effects on the Oxide of SOI MOSFET under Off-State TDDB Degradation: RF Characterization and Modeling.

Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device's impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation.

Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed.

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate-drain capacitance (Cgd) and gate-drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

High-Temperature and High-Electron Mobility Metal-Oxide-Semiconductor Field-Effect Transistors Based on N-Type Diamond.

Diamond holds the highest figure-of-merits among all the known semiconductors for next-generation electronic devices far beyond the performance of conventional semiconductor silicon. To realize diamond integrated circuits, both n- and p-channel conductivity are required for the development of diamond complementary metal-oxide-semiconductor (CMOS) devices, as those established for semiconductor silicon. However, diamond CMOS has never been achieved due to the challenge in n-type channel MOS field-effect transistors (MOSFETs). Here, electronic-grade phosphorus-doped n-type diamond epilayer with an atomically flat surface based on step-flow nucleation mode is fabricated. Consequently, n-channel diamond MOSFETs are demonstrated. The n-type diamond MOSFETs exhibit a high field-effect mobility around 150 cm2 V-1 s-1 at 573 K, which is the highest among all the n-channel MOSFETs based on wide-bandgap semiconductors. This work enables the development of energy-efficient and high-reliability CMOS integrated circuits for high-power electronics, integrated spintronics, and extreme sensors under harsh environments.

Analysis of Lanthanum Oxide Based Double-Gate SOI MOSFET using Monte-Carlo Process.

INTRODUCTION: This work proposes a Double-Gate (DG) MOSFET with a Single Material made of Silicon On-Insulator (SOI). The Lanthanum Oxide material with a high k-dielectric constant has been used as an interface between two gates and the channel. The Monte Carlo analysis has been used to determine the Conduction Band Energy (Ec) profiles and electron sheet carrier densities (ns) for a Silicon channel thickness (tsi) of 10 nm at 0.5 V gate drain-source voltages. The transverse electric fields are weak at the midchannel of DG SOI MOSFETs, where quantum effects are encountered. The Monte Carlo simulation has been confirmed to be effective for high-energy transport. A particle description reproduces the granularity property of the transport for nanoscale modeling. METHODS: This work utilizes a Monte Carlo (MC) Simulation for the proposed Double Gate Single Material Silicon On Insulator MOSFET with (La2O3=2 nm) as dielectric oxide on upper and lower gate material. The electrical properties of the DG SOI MOSFETs with Lanthanum Oxide were analyzed using Monte Carlo simulation, including the conduction band energy, electric field, potential distribution, particle movement, and average velocity. RESULTS: The peak electric field (E) simulation results and an average drift velocity (υavg) of 6Í105 V/cm and 1.6Í107 cm/s were obtained, respectively. The conduction band energy for the operating region of the source has been observed to be 4 % to the drain side, which obtained a value of -0.04 eV at the terminal end. CONCLUSION: This proposed patent design, such as double-gate SOI-based devices, is the best suggestion for significant scalability challenges. Emerging technologies reach the typical DG SOI MOSFET's threshold performance when their geometrical dimensions are in the nanometer region. This device based on nanomaterial compounds has been more submissive than conventional devices. The nanomaterials usage in the design is more suitable for downscaling and reducing packaging density.

The Understanding and Compact Modeling of Reliability in Modern Metal-Oxide-Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms.

With the technological scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

A 2.8 kV Breakdown Voltage α-Ga2O3 MOSFET with Hybrid Schottky Drain Contact.

Among various polymorphic phases of gallium oxide (Ga2O3), α-phase Ga2O3 has clear advantages such as its heteroepitaxial growth as well as wide bandgap, which is promising for use in power devices. In this work, we demonstrate α-Ga2O3 MOSFETs with hybrid Schottky drain (HSD) contact, comprising both Ohmic and Schottky electrode regions. In comparison with conventional Ohmic drain (OD) contact, a lower on-resistance (Ron) of 2.1 kΩ mm is achieved for variable channel lengths. Physics-based TCAD simulation is performed to validate the turn-on characteristics of the Schottky electrode region and the improved Ron. Electric-field analysis in the off-state is conducted for both the OD and HSD devices. Furthermore, a record breakdown voltage (BV) of 2.8 kV is achieved, which is superior to the 1.7 kV of the compared OD device. Our results show that the proposed HSD contact with a further optimized design can be a promising drain electrode scheme for α-Ga2O3 power MOSFETs.

A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique.

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.