Can Older Adult Patients with Hip Fractures Have Their Discharge Destination Predicted by Physical Performance Measures?

Background and Objectives: The majority of patients who undergo hip fracture surgery do not recover their former level of physical function; hence, it is essential to establish a specific rehabilitation strategy for maximal functional recovery of patients after a hip fracture. Knowing which indicators of physical function in hip fracture patients have a significant impact on the decision regarding the place or timing of discharge would make it possible to plan and prepare for discharge as soon as possible. Therefore, this study aimed to investigate the relationship between physical function and discharge destination for older adult patients with hip fracture. Materials and Methods: In this retrospective cohort study, 150 hip fracture patients (mean age 78.9 ± 10.6 years) between January 2019 and June 2021 were enrolled. Patients were categorized into two groups according to their discharge destination, either home or facility. Demographic and disease-related characteristic data were collected from the medical records. All the patients completed performance-based physical function tests including the 10 Meter Walk Test (10MWT), Timed Up and Go test (TUG), Koval's grade, and Berg Balance Scale (BBS) at the start of rehabilitation and at discharge. A backward stepwise binary logistic regression analysis was then performed to determine the independent factors of the discharge destination. Results: The home discharge group had a significantly lower Koval's grade, lower TUG, higher BBS both at baseline and discharge, and younger age. Backward stepwise logistic binary regression analysis showed that TUG, BBS, and 10MWT at baseline and discharge were significant variables affecting the discharge destination after hip fracture. Conclusions: These results demonstrate that balance and gait in older adult patients with hip fractures are highly influential factors in the determining the discharge destination.

Highly parallel and ultra-low-power probabilistic reasoning with programmable gaussian-like memory transistors.

Probabilistic inference in data-driven models is promising for predicting outputs and associated confidence levels, alleviating risks arising from overconfidence. However, implementing complex computations with minimal devices still remains challenging. Here, utilizing a heterojunction of p- and n-type semiconductors coupled with separate floating-gate configuration, a Gaussian-like memory transistor is proposed, where a programmable Gaussian-like current-voltage response is achieved within a single device. A separate floating-gate structure allows for exquisite control of the Gaussian-like current output to a significant extent through simple programming, with an over 10000 s retention performance and mechanical flexibility. This enables physical evaluation of complex distribution functions with the simplified circuit design and higher parallelism. Successful implementation for localization and obstacle avoidance tasks is demonstrated using Gaussian-like curves produced from Gaussian-like memory transistor. With its ultralow-power consumption, simplified design, and programmable Gaussian-like outputs, our 3-terminal Gaussian-like memory transistor holds potential as a hardware platform for probabilistic inference computing.