DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy.

This study developed a DC-free technique that used dark-mode scanning capacitance microscopy (DM-SCM) with a small-area contact electrode to evaluate and image equivalent oxide thicknesses (EOTs). In contrast to the conventional capacitance-voltage (C-V) method, which requires a large-area contact electrode and DC voltage sweeping to provide reliable C-V curves from which the EOT can be determined, the proposed method enabled the evaluation of the EOT to a few nanometers for thermal and high-k oxides. The signal intensity equation defining the voltage modulation efficiency in scanning capacitance microscopy (SCM) indicates that thermal oxide films on silicon can serve as calibration references for the establishment of a linear relationship between the SCM signal ratio and the EOT ratio; the EOT is then determined from this relationship. Experimental results for thermal oxide films demonstrated that the EOT obtained using the DM-SCM approach closely matched the value obtained using the typical C-V method for frequencies ranging from 90 kHz to 1 MHz. The percentage differences in EOT values between the C-V and SCM measurements were smaller than 0.5%. For high-k oxide films, DM-SCM with a DC-free operation may mitigate the effect of DC voltages on evaluations of EOTs. In addition, image operations were performed to obtain EOT images showing the EOT variation induced by DC-stress-induced charge trapping. Compared with the typical C-V method, the proposed DM-SCM approach not only provides a DC-free approach for EOT evaluation, but also offers a valuable opportunity to visualize the EOT distribution before and after the application of DC stress.

Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode.

In this work, the ferroelectric characteristic of a 5 nm Hf0.5Zr0.5O2 (HZO) metal-ferroelectric-insulator-semiconductor (MFIS) device is enhanced through strained complementary metal oxide semiconductor (CMOS)-compatible TiN electrode engineering. Strained TiN top-layer electrodes with different nitrogen (N) concentrations are deposited by adjusting the sputtering process conditions. The TiN electrode with 18% N exhibits a compressive characteristic, which induces tensile stress in a 5 nm HZO film. A device with 18% N in TiN shows a higher remanent polarization (2Pr) and larger capacitance value than the compared sample, indicating that the strained TiN is promising for enhancing the ferroelectricity of sub-5 nm HZO devices.

Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations.

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS2 FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.

Steep-slope hysteresis-free negative capacitance MoS2 transistors.

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 µA µm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique.

In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al.

A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires.

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

Novel poly-silicon nanowire field effect transistor for biosensing application.

A simple and low-cost method to fabricate poly-silicon nanowire field effect transistor (poly-Si NW FET) for biosensing application was demonstrated. The poly-silicon nanowire (poly-Si NW) channel was fabricated by employing the poly-silicon (poly-Si) sidewall spacer technique, which approach was comparable with current commercial semiconductor process and forsaken expensive E-beam lithography tools. The electronic properties of the poly-Si NW FET in aqueous solution were found to be similar to those of single-crystal silicon nanowire field effect transistors reported in the literature. A model biotin and avidin/streptavidin sensing system was used to demonstrate the biosensing capacity of poly-Si NW FET. The changes of I(D)-V(G) curves were consistent with an n-type FET affected by a nearby negatively (streptavidin) and positively (avidin) charged molecules, respectively. Specific electric changes were observed for streptavidin and avidin sensing when nanowire surface of poly-Si NW FET was modified with biotin and streptavidin at sub pM to nM range could be distinguished. With its excellent electric properties and the potential for mass commercial production, poly-Si NW FET can be a very useful transducer for a variety of biosensing applications.

Ultrasensitive detection of dopamine using a polysilicon nanowire field-effect transistor.

An unprecedented high sensitive sensing of neurotransmitter dopamine at fM level was demonstrated using a poly-crystalline silicon nanowire field-effect transistor (poly-SiNW FET) fabricated by employing a simple and low-cost poly-Si sidewall spacer technique, which was compatible with current commercial semiconductor processes for large-scale standard manufacture.