Controlled Growth of a Large-Size 2D Selenium Nanosheet and Its Electronic and Optoelectronic Applications.

Selenium has attracted intensive attention as a promising material candidate for future optoelectronic applications. However, selenium has a strong tendency to grow into nanowire forms due to its anisotropic atomic structure, which has largely hindered the exploration of its potential applications. In this work, using a physical vapor deposition method, we have demonstrated the synthesis of large-size, high-quality 2D selenium nanosheets, the minimum thickness of which could be as thin as 5 nm. The Se nanosheet exhibits a strong in-plane anisotropic property, which is determined by angle-resolved Raman spectroscopy. Back-gating field-effect transistors based on a Se nanosheet exhibit p-type transport behaviors with on-state current density around 20 mA/mm at Vds = 3 V. Four-terminal field-effect devices are also fabricated to evaluate the intrinsic hole mobility of the selenium nanosheet, and the value is determined to be 0.26 cm2 V-1 s-1 at 300 K. The selenium nanosheet phototransistors show an excellent photoresponsivity of up to 263 A/W, with a rise time of 0.1 s and fall time of 0.12 s. These results suggest that crystal selenium as a 2D form of a 1D van der Waals solid opens up the possibility to explore device applications.

ß-Ga2O3 Nanomembrane Negative Capacitance Field-Effect Transistors with Steep Subthreshold Slope for Wide Band Gap Logic Applications.

Steep-slope ß-Ga2O3 nanomembrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in the gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate-voltage sweeps with a minimum value of 34.3 mV/dec at the reverse gate-voltage sweep and 53.1 mV/dec at the forward gate-voltage sweep at V DS = 0.5 V. Enhancement-mode operation with a threshold voltage of ∼0.4 V is achieved by tuning the thickness of the ß-Ga2O3 membrane. Low hysteresis of less than 0.1 V is obtained. The steep-slope, low hysteresis, and enhancement-mode ß-Ga2O3 NC-FETs are promising as an nFET candidate for future wide band gap complementary metal-oxide-semiconductor logic applications.

How Important Is the Metal-Semiconductor Contact for Schottky Barrier Transistors: A Case Study on Few-Layer Black Phosphorus?

Black phosphorus (BP) is a recently rediscovered layered two-dimensional (2D) semiconductor with a direct band gap (0.35-2 eV), high hole mobility (300-5000 cm2/Vs), and transport anisotropy. In this paper, we systematically investigated the effects of metal-semiconductor interface/contacts on the performance of BP Schottky barrier transistors. First, a "clean" metal-BP contact is formed with boron nitride (BN) passivation. It is found that the contact resistance of the clean metal-BP contact is seven times less than the previously reported values. As a result, high-performance top-gate BP transistors show a record high ON-state drain current (I on) of 940 µA/µm. Second, BN tunneling barriers are formed at the source/drain contacts to help understand the abnormally high OFF-state drain current (I off) in devices with clean metal-BP contacts. This high I off is attributed to the electron tunneling current from the drain to the channel. Finally, the I on/I off of BP field-effect transistors can be significantly improved by using an asymmetric contact structure. By inserting a thin BN tunneling barrier at the drain side, I off is reduced by a factor of ∼120 with a cost of 20% reduction in I on. This case study of contacts on BP reveals the importance of understanding the metal-semiconductor contacts for 2D Schottky barrier transistors in general.

Surface chemistry of black phosphorus under a controlled oxidative environment.

Black phosphorus (BP), the bulk counterpart of monolayer phosphorene, is a relatively stable phosphorus allotrope at room temperature. However, monolayer phosphorene and ultra-thin BP layers degrade in ambient atmosphere. In this paper, we report the investigation of BP oxidation and discuss the reaction mechanism based on the x-ray photoelectron spectroscopy (XPS) data. The kinetics of BP oxidation was examined under various well-controlled conditions, namely in 5% O2/Ar, 2.3% H2O/Ar, and 5% O2 and 2.3% H2O/Ar. At room temperature, the BP surface is demonstrated not to be oxidized at a high oxidation rate in 5% O2/Ar nor in 2.3% H2O/Ar, according to XPS, with the thickness of the oxidized phosphorus layer <5 Å for 5 h. On the other hand, in the O2/H2O mixture, a 30 Å thickness oxide layer was detected already after 2 h of the treatment. This result points to a synergetic effect of water and oxygen in the BP oxidation. The oxidation effect was also studied in applications to the electrical measurements of BP field-effect transistors (FETs) with or without passivation. The electrical performance of BP FETs with atomic layer deposition (ALD) dielectric passivation or h-BN passivation formed in a glove-box environment are also presented.

Mechanisms of current fluctuation in ambipolar black phosphorus field-effect transistors.

Multi-layer black phosphorus has emerged as a strong candidate owing to its high carrier mobility with most of the previous research work focused on its p-type properties. Very few studies have been performed on its n-type electronic characteristics which are important not only for the complementary operation for logic, but also crucial for understanding the carrier transport through the metal-black phosphorus junction. A thorough understanding and proper evaluation of the performance potential of both p- and n-types are highly desirable. In this paper, we investigate the temperature dependent ambipolar operation of both electron and hole transport from 300 K to 20 K. On-currents as high as 85 µA µm(-1) for a 0.2 µm channel length BP nFET at 300 K are observed. Moreover, we provide the first systematic study on the low frequency noise mechanisms for both n-channel and p-channel BP transistors. The dominated noise mechanisms of the multi-layer BP nFET and pFET are mobility fluctuation and carrier number fluctuations with correlated mobility fluctuations, respectively. We have also established a baseline of the low electrical noise of 8.1 × 10(-9)µm(2) Hz(-1) at 10 Hz at room temperature for BP pFETs, which is 3 times improvement over previous reports, and 7.0 × 10(-8)µm(2) Hz(-1) for BP nFETs for the first time.

Nanomanufacturing of 2D Transition Metal Dichalcogenide Materials Using Self-Assembled DNA Nanotubes.

2D transition metal dichalcogenides (TMDCs) are nanomanufactured using a generalized strategy with self-assembled DNA nanotubes. DNA nanotubes of various lengths serve as lithographic etch masks for the dry etching of TMDCs. The nanostructured TMDCs are studied by atomic force microscopy, photoluminescence, and Raman spectroscopy. This parallel approach can be used to manufacture 2D TMDC nanostructures of arbitrary geometries with molecular-scale precision.

Performance potential and limit of MoS2 transistors.

High-performance MoS2 transistors scaled down to 100 nm are studied at various temperatures down to 20 K, where a highest drive current of 800 µA µm(-1) can be achieved. Extremely low electrical noise of 2.8 × 10(-10) µm(2) Hz(-1) at 10 Hz is also achieved at room temperature. Furthermore, a negative differential resistance behavior is experimentally observed and its origin of self-heating is identified using pulsed-current-voltage measurements.

Chloride molecular doping technique on 2D materials: WS2 and MoS2.

Low-resistivity metal-semiconductor (M-S) contact is one of the urgent challenges in the research of 2D transition metal dichalcogenides (TMDs). Here, we report a chloride molecular doping technique which greatly reduces the contact resistance (Rc) in the few-layer WS2 and MoS2. After doping, the Rc of WS2 and MoS2 have been decreased to 0.7 kΩ·µm and 0.5 kΩ·µm, respectively. The significant reduction of the Rc is attributed to the achieved high electron-doping density, thus a significant reduction of Schottky barrier width. As a proof-of-concept, high-performance few-layer WS2 field-effect transistors (FETs) are demonstrated, exhibiting a high drain current of 380 µA/µm, an on/off ratio of 4 × 10(6), and a peak field-effect mobility of 60 cm(2)/(V·s). This doping technique provides a highly viable route to diminish the Rc in TMDs, paving the way for high-performance 2D nanoelectronic devices.