Your browser doesn't support javascript.
loading
Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology.
Noh, Changwoo; Han, Changwoo; Won, Sang Min; Shin, Changhwan.
Affiliation
  • Noh C; Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon 16419, Korea.
  • Han C; Semiconductor R&D Center, Samsung Electronics, Hwasung 18448, Korea.
  • Won SM; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
  • Shin C; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
Micromachines (Basel) ; 13(9)2022 Sep 19.
Article in En | MEDLINE | ID: mdl-36144174
Key words
Fulltext
Add to My VHL
Print
XML
PubMed Links
Search on Google

Full text: 1 Collection: 01-internacional Database: MEDLINE Language: En Journal: Micromachines (Basel) Year: 2022 Document type: Article Country of publication: Suiza
Fulltext
Add to My VHL
Print
XML
PubMed Links
Search on Google

Full text: 1 Collection: 01-internacional Database: MEDLINE Language: En Journal: Micromachines (Basel) Year: 2022 Document type: Article Country of publication: Suiza