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Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory.
Liu, Xiwen; Wang, Dixiong; Kim, Kwan-Ho; Katti, Keshava; Zheng, Jeffrey; Musavigharavi, Pariasadat; Miao, Jinshui; Stach, Eric A; Olsson, Roy H; Jariwala, Deep.
Affiliation
  • Liu X; Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Wang D; Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Kim KH; Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Katti K; Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Zheng J; Material Science and Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Musavigharavi P; Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Miao J; Material Science and Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Stach EA; Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Olsson RH; Material Science and Engineering, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
  • Jariwala D; Laboratory for Research on the Structure of Matter, University of Pennsylvania, Philadelphia, Pennsylvania 19104, United States.
Nano Lett ; 21(9): 3753-3761, 2021 May 12.
Article in En | MEDLINE | ID: mdl-33881884
Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.
Key words

Full text: 1 Collection: 01-internacional Database: MEDLINE Language: En Journal: Nano Lett Year: 2021 Document type: Article Affiliation country: United States Country of publication: United States

Full text: 1 Collection: 01-internacional Database: MEDLINE Language: En Journal: Nano Lett Year: 2021 Document type: Article Affiliation country: United States Country of publication: United States