Extending High-Level Synthesis for Task-Parallel Programs.
Proc Annu IEEE Symp Field Program Cust Comput Mach
; 20212021 May.
Article
en En
| MEDLINE
| ID: mdl-34497978
ABSTRACT
C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of results (QoR) and short development cycles compared with the traditional register-transfer level design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools do support task-parallel programs, the productivity is greatly limited â in the code development cycle due to the poor programmability, â¡ in the correctness verification cycle due to restricted software simulation, and ⢠in the QoR tuning cycle due to slow code generation. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA accelerators. In this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, unconstrained software simulation, and fast hierarchical code generation to overcome these limitations and demonstrate how task-parallel programs can be productively supported in HLS. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly shortened by 3.2× and 6.8×, respectively. Our work is open-source at https//github.com/UCLA-VAST/tapa/.
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01-internacional
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MEDLINE
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En
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Proc Annu IEEE Symp Field Program Cust Comput Mach
Año:
2021
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Article