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Precise and low-power closed-loop neuromodulation through algorithm-integrated circuit co-design.
Yang, Jie; Zhao, Shiqi; Wang, Junzhe; Lin, Siyu; Hou, Qiming; Sawan, Mohamad.
Afiliación
  • Yang J; CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou, China.
  • Zhao S; CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou, China.
  • Wang J; CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou, China.
  • Lin S; CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou, China.
  • Hou Q; CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou, China.
  • Sawan M; CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou, China.
Front Neurosci ; 18: 1340164, 2024.
Article en En | MEDLINE | ID: mdl-38550560
ABSTRACT
Implantable neuromodulation devices have significantly advanced treatments for neurological disorders such as Parkinson's disease, epilepsy, and depression. Traditional open-loop devices like deep brain stimulation (DBS) and spinal cord stimulators (SCS) often lead to overstimulation and lack adaptive precision, raising safety and side-effect concerns. Next-generation closed-loop systems offer real-time monitoring and on-device diagnostics for responsive stimulation, presenting a significant advancement for treating a range of brain diseases. However, the high false alarm rates of current closed-loop technologies limit their efficacy and increase energy consumption due to unnecessary stimulations. In this study, we introduce an artificial intelligence-integrated circuit co-design that targets these issues and using an online demonstration system for closed-loop seizure prediction to showcase its effectiveness. Firstly, two neural network models are obtained with neural-network search and quantization strategies. A binary neural network is optimized for minimal computation with high sensitivity and a convolutional neural network with a false alarm rate as low as 0.1/h for false alarm rejection. Then, a dedicated low-power processor is fabricated in 55 nm technology to implement the two models. With reconfigurable design and event-driven processing feature the resulting application-specific integrated circuit (ASIC) occupies only 5mm2 silicon area and the average power consumption is 142 µW. The proposed solution achieves a significant reduction in both false alarm rates and power consumption when benchmarked against state-of-the-art counterparts.
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Texto completo: 1 Colección: 01-internacional Base de datos: MEDLINE Idioma: En Revista: Front Neurosci Año: 2024 Tipo del documento: Article País de afiliación: China Pais de publicación: Suiza

Texto completo: 1 Colección: 01-internacional Base de datos: MEDLINE Idioma: En Revista: Front Neurosci Año: 2024 Tipo del documento: Article País de afiliación: China Pais de publicación: Suiza