A Novel, Low Computational Complexity, Parallel Swarm Algorithm for Application in Low-Energy Devices.

In this work, we propose a novel metaheuristic algorithm that evolved from a conventional particle swarm optimization (PSO) algorithm for application in miniaturized devices and systems that require low energy consumption. The modifications allowed us to substantially reduce the computational complexity of the PSO algorithm, translating to reduced energy consumption in hardware implementation. This is a paramount feature in the devices used, for example, in wireless sensor networks (WSNs) or wireless body area sensors (WBANs), in which particular devices have limited access to a power source. Various swarm algorithms are widely used in solving problems that require searching for an optimal solution, with simultaneous occurrence of a different number of sub-optimal solutions. This makes the hardware implementation worthy of consideration. However, hardware implementation of the conventional PSO algorithm is challenging task. One of the issues is an efficient implementation of the randomization function. In this work, we propose novel methods to work around this problem. In the proposed approach, we replaced the block responsible for generating random values using deterministic methods, which differentiate the trajectories of particular particles in the swarm. Comprehensive investigations in the software model of the modified algorithm have shown that its performance is comparable with or even surpasses the conventional PSO algorithm in a multitude of scenarios. The proposed algorithm was tested with numerous fitness functions to verify its flexibility and adaptiveness to different problems. The paper also presents the hardware implementation of the selected blocks that modify the algorithm. In particular, we focused on reducing the hardware complexity, achieving high-speed operation, while reducing energy consumption.

Impact of Hepatic Artery Variations and Reconstructions on the Outcome of Orthotopic Liver Transplantation.

BACKGROUND: Donor variational arteries often require complex reconstruction. METHODS: We analysed the incidence of different variations, types of arterial reconstructions and their impact on post-operative results from 409 patients undergoing liver transplantation at Karolinska Institute between 2007 and 2015. RESULTS: A total of 292 (71.4%) liver grafts had a standard hepatic artery (SHA), and 117 (28.6%) showed hepatic artery variants (HAV). 58% of HAV needed reconstruction. The main variations were variant left hepatic artery (45.3%) from the gastric artery; variant right hepatic artery (38.5%); and a triple combination of variant right and left hepatic artery and the proper hepatic artery from the common hepatic artery (12.8%); other 3.4%. Patients/graft survival and arterial complications were not different between SHA and HAV. Incidence of biliary stricture was numerically higher in left hepatic artery variants (p = 0.058) and in variants where no arterial reconstruction was performed (p = 0.001). Operation and arterial warm ischaemia time were longer in the HAV group. The need for intraoperative re-reconstruction was higher in the HAV group (p = 0.04). Intraoperative bleeding was larger after back-table reconstruction than with intraoperative reconstruction (p = 0.04). CONCLUSION: No overall differences were found between the HAV and the SHA groups. Occurrence of a variant left hepatic artery and HAV with no reconstruction seems to increase the risk of biliary strictures.

First European Case of Simultaneous Liver and Pancreas Transplantation as Treatment of Wolcott-Rallison Syndrome in a Small Child.

BACKGROUND: The concept of organ transplantation as treatment for complex genetic conditions, including Wolcott-Rallison syndrome (WRS), continues to show promise. Liver transplantation is essential for survival of patients with WRS, and pancreas transplantation cures their type I diabetes mellitus. METHODS: The recipient, a 3-year-old girl weighing 14 kg at the time of transplantation, suffered from major complications of WRS, including repetitive liver failure episodes and poorly controlled diabetes. The patient underwent a nonacute, combined, simultaneous liver and pancreas transplantation from a pediatric donor without using the en bloc technique. RESULTS: Well-preserved graft functions at 2-year follow-up with normal liver and pancreas function. CONCLUSIONS: This is the first case report of simultaneous liver and pancreas transplantation as treatment of WRS in a small child in Europe. Two-year follow-up demonstrates that organ transplantation can halt life-threating recurrent liver failure episodes and cure type 1 diabetes.

Novel techniques for a wireless motion capture system for the monitoring and rehabilitation of disabled persons for application in smart buildings.

BACKGROUND: Due to the problem of aging societies, there is a need for smart buildings to monitor and support people with various disabilities, including rheumatoid arthritis. OBJECTIVE: The aim of this paper is to elaborate on novel techniques for wireless motion capture systems for the monitoring and rehabilitation of disabled people for application in smart buildings. METHODS: The proposed techniques are based on cross-verification of distance measurements between markers and transponders in an environment with highly variable parameters. To their verification, algorithms that enable comprehensive investigation of a system with different numbers of transponders and varying ambient parameters (temperature and noise) were developed. In the estimation of the real positions of markers, various linear and nonlinear filters were used. Several thousand tests were carried out for various system parameters and different marker locations. RESULTS: The results show that localization error may be reduced by as much as 90%. It was observed that repetition of measurements reduces localization error by as much as one order of magnitude. CONCLUSIONS: The proposed system, based on wireless techniques, offers a high commercial potential. However, it requires extensive cooperation between teams, including hardware and software design, system modelling, and architectural design.

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology.

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18- [Formula: see text] technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 µm(2). When operating in the L2 mode, the circuit dissipates 85 [Formula: see text] of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 [Formula: see text] from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip.

An efficient transistor level implementation of a flexible, programmable triangular function (TF) that can be used as a triangular neighborhood function (TNF) in ultra-low power, self-organizing maps (SOMs) realized as application-specific integrated circuit (ASIC) is presented. The proposed TNF block is a component of a larger neighborhood mechanism, whose role is to determine the distance between the winning neuron and all neighboring neurons. Detailed simulations carried out for the software model of such network show that the TNF forms a good approximation of the gaussian neighborhood function (GNF), while being implemented in a much easier way in hardware. The overall mechanism is very fast. In the CMOS 0.18 µm technology, distances to all neighboring neurons are determined in parallel, within the time not exceeding 11 ns, for an example neighborhood range, R, of 15. The TNF blocks in particular neurons require another 6 ns to calculate the output values directly used in the adaptation process. This is also performed in parallel in all neurons. As a result, after determining the winning neuron, the entire map is ready for the adaptation after the time not exceeding 17 ns, even for large numbers of neurons. This feature allows for the realization of ultra low power SOMs, which are hundred times faster than similar SOMs realized on PC. The signal resolution at the output of the TNF block has a dominant impact on the overall energy consumption as well as the silicon area. Detailed system level simulations of the SOM show that even for low resolutions of 3 to 6 bits, the learning abilities of the SOM are not affected. The circuit performance has been verified by means of transistor level Hspice simulations carried out for different transistor models and different values of supply voltage and the environment temperature - a typical procedure completed in case of commercial chips that makes the obtained results reliable.

Parallel programmable asynchronous neighborhood mechanism for Kohonen SOM implemented in CMOS technology.

We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. The mechanism is very fast. In a medium sized map with several hundreds neurons implemented in the complementary metal-oxide semiconductor 0.18 µm technology, all neurons start adapting the weights after no more than 11 ns. The adaptation is then carried out in parallel. This is an evident advantage in comparison with the commonly used software-realized SOMs. The circuit is robust against the process, supply voltage and environment temperature variations. Due to a simple structure, it features low energy consumption of a few pJ per neuron per a single learning pattern. In this paper, we discuss different aspects of hardware realization, such as a suitable selection of the map topology and the initial neighborhood range, as the optimization of these parameters is essential when looking from the circuit complexity point of view. For the optimal values of these parameters, the chip area and the power dissipation can be reduced even by 60% and 80%, respectively, without affecting the quality of learning.