Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management.

Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm²), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

Opportunities for Electroceuticals in Epilepsy.

Epilepsy is a neurological disorder that affects ∼1% of the world population. Nearly 30% of epilepsy patients suffer from pharmacoresistant epilepsy that cannot be treated with antiepileptic drugs. Depending on seizure type, a diverse range of therapies are available, including surgery, vagus nerve stimulation, and deep brain stimulation. We review the sensing and stimulation technologies most used in neurological disorders, and provide a vision of minimally invasive electroceuticals to enable accurate forecasting of epileptic seizures and therapy. The use of such systems could potentially help patients to prevent injuries and, in combination with an intervention mechanism, could provide a method of suppressing seizures in epileptic patients.

Investigation of Event-Based Surfaces for High-Speed Detection, Unsupervised Feature Extraction, and Object Recognition.

In this work, we investigate event-based feature extraction through a rigorous framework of testing. We test a hardware efficient variant of Spike Timing Dependent Plasticity (STDP) on a range of spatio-temporal kernels with different surface decaying methods, decay functions, receptive field sizes, feature numbers, and back end classifiers. This detailed investigation can provide helpful insights and rules of thumb for performance vs. complexity trade-offs in more generalized networks, especially in the context of hardware implementation, where design choices can incur significant resource costs. The investigation is performed using a new dataset consisting of model airplanes being dropped free-hand close to the sensor. The target objects exhibit a wide range of relative orientations and velocities. This range of target velocities, analyzed in multiple configurations, allows a rigorous comparison of time-based decaying surfaces (time surfaces) vs. event index-based decaying surface (index surfaces), which are used to perform unsupervised feature extraction, followed by target detection and recognition. We examine each processing stage by comparison to the use of raw events, as well as a range of alternative layer structures, and the use of random features. By comparing results from a linear classifier and an ELM classifier, we evaluate how each element of the system affects accuracy. To generate time and index surfaces, the most commonly used kernels, namely event binning kernels, linearly, and exponentially decaying kernels, are investigated. Index surfaces were found to outperform time surfaces in recognition when invariance to target velocity was made a requirement. In the investigation of network structure, larger networks of neurons with large receptive field sizes were found to perform best. We find that a small number of event-based feature extractors can project the complex spatio-temporal event patterns of the dataset to an almost linearly separable representation in feature space, with best performing linear classifier achieving 98.75% recognition accuracy, using only 25 feature extracting neurons.

A FPGA Implementation of the CAR-FAC Cochlear Model.

This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

Instantaneous VO2 from a wearable device.

We present a method for calculating instantaneous oxygen uptake (VO2) through the use of a non-invasive and non-obtrusive (i.e. without a face mask) wearable device, together with its clinical evaluation against a standard technique based upon expired gas calorimetry. This method can be integrated with existing wearable devices, we implemented it in the "Device for Reliable Energy Expenditure Monitoring" (DREEM). The DREEM comprises a single lead electrocardiogram (ECG) device combined with a tri-axial accelerometer and is worn around the waist. Our clinical evaluation tests the developed method against a gold standard for VO2, expired gas calorimetry, using an ethically approved protocol comprising active exercise and sedentary periods. The study was performed on 42 participants from a wide sample population including healthy people, athletes and an at-risk health group including persons affected by obesity. We developed an algorithm combining heart rate (HR) and the integral of absolute acceleration (IAA), with results showing a correlation of r = 0.93 for instantaneous VO2, and r = 0.97 for 3 min mean VO2, this is a considerably improved estimation of VO2 in comparison to methods utilising HR and IAA independently.

Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition.

We present a hardware architecture that uses the neural engineering framework (NEF) to implement large-scale neural networks on field programmable gate arrays (FPGAs) for performing massively parallel real-time pattern recognition. NEF is a framework that is capable of synthesising large-scale cognitive systems from subnetworks and we have previously presented an FPGA implementation of the NEF that successfully performs nonlinear mathematical computations. That work was developed based on a compact digital neural core, which consists of 64 neurons that are instantiated by a single physical neuron using a time-multiplexing approach. We have now scaled this approach up to build a pattern recognition system by combining identical neural cores together. As a proof of concept, we have developed a handwritten digit recognition system using the MNIST database and achieved a recognition rate of 96.55%. The system is implemented on a state-of-the-art FPGA and can process 5.12 million digits per second. The architecture and hardware optimisations presented offer high-speed and resource-efficient means for performing high-speed, neuromorphic, and massively parallel pattern recognition and classification tasks.

A 0.04 mm (2) Buck-Boost DC-DC Converter for Biomedical Implants Using Adaptive Gain and Discrete Frequency Scaling Control.

This paper presents the design of a reconfigurable buck-boost switched-capacitor DC-DC converter suitable for use in a wide range of biomedical implants. The proposed converter has an extremely small footprint and uses a novel control method that allows coarse and fine control of the output voltage. The converter uses adaptive gain control, discrete frequency scaling and pulse-skipping schemes to regulate the power delivered to a range of output voltages and loads. Adaptive gain control is used to implement variable switching gain ratios from a reconfigurable power stage and thereby make coarse steps in output voltage. A discrete frequency scaling controller makes discrete changes in switching frequency to vary the power delivered to the load and perform fine tuning when the output voltage is within 10% of the target output voltage. The control architecture is predominately digital and it has been implemented as part of a fully-integrated switched-capacitor converter design using a standard bulk CMOS 0.18 µm process. Measured results show that the converter has an output voltage range of 1.0 to 2.2 V, can deliver up to 7.5 mW of load power and efficiency up to 75% using an active area of only 0.04 mm (2), which is significantly smaller than that of other designs. This low-area, low-complexity reconfigurable power converter can support low-power circuits in biomedical implant applications.

A novel method for non-invasive respiration monitoring.

In this paper we present an atypical method for measuring respiration volume. We infer heart rate variability (HRV) from an electrocardiogram (ECG) and present results from a pilot study of 6 participants to validate measuring respiration volume from HRV in comparison to the Cosmed K4b(2). We show a qualitative correlation and trend between the known respiration volume as measured by the Cosmed K4b(2) and the new method for measuring lung volume. From these results, we propose guidelines for an in-depth study of measuring respiration volumes from heart rate variability.

Turn Down That Noise: Synaptic Encoding of Afferent SNR in a Single Spiking Neuron.

We have added a simplified neuromorphic model of Spike Time Dependent Plasticity (STDP) to the previously described Synapto-dendritic Kernel Adapting Neuron (SKAN), a hardware efficient neuron model capable of learning spatio-temporal spike patterns. The resulting neuron model is the first to perform synaptic encoding of afferent signal-to-noise ratio in addition to the unsupervised learning of spatio-temporal spike patterns. The neuron model is particularly suitable for implementation in digital neuromorphic hardware as it does not use any complex mathematical operations and uses a novel shift-based normalization approach to achieve synaptic homeostasis. The neuron's noise compensation properties are characterized and tested on random spatio-temporal spike patterns as well as a noise corrupted subset of the zero images of the MNIST handwritten digit dataset. Results show the simultaneously learning common patterns in its input data while dynamically weighing individual afferents based on their signal to noise ratio. Despite its simplicity the interesting behaviors of the neuron model and the resulting computational power may also offer insights into biological systems.

An FPGA Implementation of a Polychronous Spiking Neural Network with Delay Adaptation.

We present an FPGA implementation of a re-configurable, polychronous spiking neural network with a large capacity for spatial-temporal patterns. The proposed neural network generates delay paths de novo, so that only connections that actually appear in the training patterns will be created. This allows the proposed network to use all the axons (variables) to store information. Spike Timing Dependent Delay Plasticity is used to fine-tune and add dynamics to the network. We use a time multiplexing approach allowing us to achieve 4096 (4k) neurons and up to 1.15 million programmable delay axons on a Virtex 6 FPGA. Test results show that the proposed neural network is capable of successfully recalling more than 95% of all spikes for 96% of the stored patterns. The tests also show that the neural network is robust to noise from random input spikes.

Silicon modeling of the Mihalas-Niebur neuron.

There are a number of spiking and bursting neuron models with varying levels of complexity, ranging from the simple integrate-and-fire model to the more complex Hodgkin-Huxley model. The simpler models tend to be easily implemented in silicon but yet not biologically plausible. Conversely, the more complex models tend to occupy a large area although they are more biologically plausible. In this paper, we present the 0.5 µm complementary metal-oxide-semiconductor (CMOS) implementation of the Mihalas-Niebur neuron model--a generalized model of the leaky integrate-and-fire neuron with adaptive threshold--that is able to produce most of the known spiking and bursting patterns that have been observed in biology. Our implementation modifies the original proposed model, making it more amenable to CMOS implementation and more biologically plausible. All but one of the spiking properties--tonic spiking, class 1 spiking, phasic spiking, hyperpolarized spiking, rebound spiking, spike frequency adaptation, accommodation, threshold variability, integrator and input bistability--are demonstrated in this model.

Neuromorphic silicon neuron circuits.

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.