Polarity-Tunable Photocurrent through Band Alignment Engineering in a High-Speed WSe2/SnSe2 Diode with Large Negative Responsivity.

Excellent light-matter interaction and a wide range of thickness-tunable bandgaps in layered vdW materials coupled by the facile fabrication of heterostructures have enabled several avenues for optoelectronic applications. Realization of high photoresponsivity at fast switching speeds is a critical challenge for 2D optoelectronics to enable high-performance photodetection for optical communication. Moving away from conventional type-II heterostructure pn junctions towards a WSe2/SnSe2 type-III configuration, we leverage the steep change in tunneling current along with a light-induced heterointerface band shift to achieve high negative photoresponsivity, while the fast carrier transport under tunneling results in high speed. In addition, the photocurrent can be controllably switched from positive to negative values, with ∼104× enhancement in responsivity, by engineering the band alignment from type-II to type-III using either the drain or the gate bias. This is further reinforced by electric-field dependent interlayer band structure calculations using density functional theory. The high negative responsivity of 2 × 104 A/W and fast response time of ∼1 µs coupled with a polarity-tunable photocurrent can lead to the development of next-generation multifunctional optoelectronic devices.

Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS2 Field-Effect Transistors.

Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS2 channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS2 FETs using a gate-drain underlap design to induce a differential response from traps near the MoS2-HfO2 channel-gate dielectric interface, also referred to as border traps, to applied gate bias. The appearance of trap-driven anticlockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS2 channel flake. The underlap design also enables room temperature tuning of the anticlockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 °C, and 65 °C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO2 traps to the clockwise and anticlockwise hysteresis.

All-Electrical High-Sensitivity, Low-Power Dual-Mode Gas Sensing and Recovery with a WSe2/MoS2 pn Heterodiode.

Two-dimensional MoS2 gas sensors have conventionally relied on a change in field-effect-transistor (FET) channel resistance or in the Schottky contact/pn homojunction barrier. We demonstrate an enhancement in sensitivity (6×) and dynamic response along with a reduction in detection limit (8×) and power (104×) in a gate-tunable type-II WSe2(p)/MoS2(n) heterodiode gas sensor over an MoS2 FET on the same flake. Measurements for varying NO2 concentration, gate bias, and MoS2 flake thickness, reinforced with first-principles calculations, indicate dual-mode operation due to (i) a series resistance-based exponential change in the high-bias thermionic current (high sensitivity), and (ii) a heterointerface carrier concentration-based linear change in near-zero-bias interlayer recombination current (low power) resulting in sub-100 µW/cm2 power consumption. Fast and gate-bias tunable recovery enables an all-electrical, room-temperature dynamic operation. Coupled with the sensing of trinitrotoluene (TNT) molecules down to 80 ppb, this study highlights the potential of the WSe2/MoS2 pn heterojunction as a simple, low-overhead, and versatile chemical-sensing platform.

Accurate Threshold Voltage Reliability Evaluation of Thin Al2O3 Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses.

Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al2O3, SiO2 equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage ( Vth) instability under negative gate bias stress at various measurement delays ( tm), stress biases ( VGSTR), temperatures ( T), and stress times ( tstr) for the first time. Thin top-gated oxide enables low VGSTR that is closer to the operating condition and ultrafast Vth measurements with low delay ( tm = 10 µs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of Vth degradation (Δ Vth) shows fast saturation at longer stress times and low-temperature activation energy. Vth instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different VGSTR and T. It is shown that measurements using larger tm show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying tm (1 ms being the lowest due to a low drain current level for thick oxide), VGSTR, and T to benchmark our top-gated results. Nonsaturating Δ Vth in the back-gated devices is shown to result from recovery artifacts due to the large tm (1 ms and greater) values. Finally, using a VGSTR and T-dependent first-order model, we show that the top-gated Al2O3 BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature.

Enhanced stability and performance of few-layer black phosphorus transistors by electron beam irradiation.

Few layer black phosphorus (BP) has recently emerged as a potential graphene analogue due to its high mobility and direct, appreciable, band gap. The fabrication and characterization of field effect transistors (FETs) involves exposure of the channel material to an electron beam (e-beam) in imaging techniques such as transmission electron microscopy (TEM) and scanning electron microscopy (SEM), and fabrication techniques like electron beam lithography (EBL). Despite this, the effect of e-beam irradiation on BP-FET performance has not been studied experimentally. In this work, we report the first experimental study on the impact of e-beam irradiation on BP-FETs. An electron beam is known to induce defects and structural changes in 2D materials like graphene, MoS2etc. resulting in the deterioration of the device quality. However, for BP-FETs, we observe an improvement in the on-current and carrier mobility (µ) along with a decrease in threshold voltage (Vth) on exposure to an e-beam with 15 keV energy for 80 seconds. These changes can be attributed to the capture of electrons by traps near the SiO2-BP interface and reduced BP surface roughness due to e-beam exposure. Hysteresis measurements and physical characterization (i.e. atomic force microscopy (AFM), X-ray photoelectron (XPS) and Raman spectroscopies) validate these mechanisms. Reduced hysteresis indicates occupation of the traps, AFM surface scans indicate reduced surface roughness and XPS data show a reduced phosphorus oxide (POx) peak immediately after exposure. Raman measurements indicate a probable structural change due to the interaction between e-beam and BP which could result in better stability.