Efficient Hardware Accelerator Design of Non-Linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM for Mobile Robots.

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot's location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot's pose in SLAM. This paper combines the non-linear optimization algorithm and CSM algorithm into an NLO-CSM (Non-linear Optimization CSM) algorithm for reducing the computation resources and the amount of computation while ensuring high calculation accuracy, and it presents an efficient hardware accelerator design of the NLO-CSM algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM hardware accelerator utilizes pipeline processing and module reusing techniques to achieve low hardware overhead, fast matching, and high energy efficiency. FPGA implementation results show that, at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 0.79 W, while it performs a scan match at 8.98 ms and 7.15 mJ per frame. The proposed design outperforms the ARM-A9 dual-core CPU implementation with a 92.74% increase and 90.71% saving in computing speed and energy consumption, respectively. It has also achieved 80.3% LUTs, 84.13% FFs, and 20.83% DSPs saving, as well as an 8.17× increase in frame rate and 96.22% improvement in energy efficiency over a state-of-the-art hardware accelerator design in the literature. ASIC implementation in 65 nm can further reduce the computing time and energy consumption per scan to 5.94 ms and 0.06 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications.

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices.

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously.

Reconfigurable Skyrmion Logic Gates.

Magnetic skyrmion, a nanosized spin texture with topological property, has become an area of significant interest due to the scientific insight that it can provide and also its potential impact on applications such as ultra-low-energy and ultra-high-density logic gates. In the quest for the reconfiguration of single logic device and the implementation of the complete logic functions, a novel reconfigurable skyrmion logic (RSL) is proposed and verified by micromagnetic simulations. Logic functions including AND, OR, NOT, NAND, NOR, XOR, and XNOR are implemented in the ferromagnetic (FM) nanotrack by virtue of various effects including spin orbit torque, skyrmion Hall effect, skyrmion-edge repulsions, and skyrmion-skyrmion collision. Different logic functions can be selected in an RSL by applying voltage to specific region(s) of the device, changing the local anisotropy energy of FM film. Material properties and geometrical scaling studies suggest RSL gates fit for energy-efficient computing as well as provide the guidelines for the design and optimization of this new logic family.

A Low Power Low Phase Noise Oscillator for MICS Transceivers.

A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 µm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 µm² area. The measured phase noise is -108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage.

Magnetoresistance oscillations in topological insulator Bi2Te3 nanoscale antidot arrays.

Nanoscale antidot arrays were fabricated on a single-crystal microflake of topological insulator Bi2Te3. The introduction of antidot arrays significantly increased the resistance of the microflake, yet the temperature dependence of the resistance remains metallic. We observed that small oscillations that are periodic in magnetic field B appeared on top of the weak anti-localization magnetoresistance. Since the electron coherence length at low temperature becomes comparable to the feature size in our device, we argued that the magnetoresistance oscillations are the manifestation of quantum interference induced by the nanostructure. Our work demonstrates that the transport of topological insulators could indeed be controlled by artificially created nanostructures, and paves the way for future technological applications of this class of materials.

PUFKEY: a high-security and high-throughput hardware true random number generator for sensor networks.

Random number generators (RNG) play an important role in many sensor network systems and applications, such as those requiring secure and robust communications. In this paper, we develop a high-security and high-throughput hardware true random number generator, called PUFKEY, which consists of two kinds of physical unclonable function (PUF) elements. Combined with a conditioning algorithm, true random seeds are extracted from the noise on the start-up pattern of SRAM memories. These true random seeds contain full entropy. Then, the true random seeds are used as the input for a non-deterministic hardware RNG to generate a stream of true random bits with a throughput as high as 803 Mbps. The experimental results show that the bitstream generated by the proposed PUFKEY can pass all standard national institute of standards and technology (NIST) randomness tests and is resilient to a wide range of security attacks.

A Sensorless Predictive Current Controlled Boost Converter by Using an EKF with Load Variation Effect Elimination Function.

To realize accurate current control for a boost converter, a precise measurement of the inductor current is required to achieve high resolution current regulating. Current sensors are widely used to measure the inductor current. However, the current sensors and their processing circuits significantly contribute extra hardware cost, delay and noise to the system. They can also harm the system reliability. Therefore, current sensorless control techniques can bring cost effective and reliable solutions for various boost converter applications. According to the derived accurate model, which contains a number of parasitics, the boost converter is a nonlinear system. An Extended Kalman Filter (EKF) is proposed for inductor current estimation and output voltage filtering. With this approach, the system can have the same advantages as sensored current control mode. To implement EKF, the load value is necessary. However, the load may vary from time to time. This can lead to errors of current estimation and filtered output voltage. To solve this issue, a load variation elimination effect elimination (LVEE) module is added. In addition, a predictive average current controller is used to regulate the current. Compared with conventional voltage controlled system, the transient response is greatly improved since it only takes two switching cycles for the current to reach its reference. Finally, experimental results are presented to verify the stable operation and output tracking capability for large-signal transients of the proposed algorithm.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 µm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Design and implementation of a RF powering circuit for RFID tags or other batteryless embedded devices.

A RF powering circuit used in radio-frequency identification (RFID) tags and other batteryless embedded devices is presented in this paper. The RF powering circuit harvests energy from electromagnetic waves and converts the RF energy to a stable voltage source. Analysis of a NMOS gate-cross connected bridge rectifier is conducted to demonstrate relationship between device sizes and power conversion efficiency (PCE) of the rectifier. A rectifier with 38.54% PCE under normal working conditions is designed. Moreover, a stable voltage regulator with a temperature and voltage optimizing strategy including adoption of a combination resistor is developed, which is able to accommodate a large input range of 4 V to 12 V and be immune to temperature variations. Latch-up prevention and noise isolation methods in layout design are also presented. Designed with the HJTC 0.25 µm process, this regulator achieves 0.04 mV/°C temperature rejection ratio (TRR) and 2.5 mV/V voltage rejection ratio (VRR). The RF powering circuit is also fabricated in the HJTC 0.25 µm process. The area of the RF powering circuit is 0.23 × 0.24 mm². The RF powering circuit is successfully integrated with ISO/IEC 15693-compatible and ISO/IEC 14443-compatible RFID tag chips.

An optimal current observer for predictive current controlled buck DC-DC converters.

In digital current mode controlled DC-DC converters, conventional current sensors might not provide isolation at a minimized price, power loss and size. Therefore, a current observer which can be realized based on the digital circuit itself, is a possible substitute. However, the observed current may diverge due to the parasitic resistors and the forward conduction voltage of the diode. Moreover, the divergence of the observed current will cause steady state errors in the output voltage. In this paper, an optimal current observer is proposed. It achieves the highest observation accuracy by compensating for all the known parasitic parameters. By employing the optimal current observer-based predictive current controller, a buck converter is implemented. The converter has a convergently and accurately observed inductor current, and shows preferable transient response than the conventional voltage mode controlled converter. Besides, costs, power loss and size are minimized since the strategy requires no additional hardware for current sensing. The effectiveness of the proposed optimal current observer is demonstrated experimentally.

In-Memory Mathematical Operations with Spin-Orbit Torque Devices.

Analog arithmetic operations are the most fundamental mathematical operations used in image and signal processing as well as artificial intelligence (AI).  In-memory computing (IMC) offers a high performance and energy-efficient computing paradigm. To date, in-memory analog arithmetic operations with emerging nonvolatile devices are usually implemented using discrete components, which limits the scalability and blocks large scale integration. Here, a prototypical implementation of in-memory analog arithmetic operations (summation, subtraction and multiplication) is experimentally demonstrated, based on in-memory electrical current sensing units using spin-orbit torque (SOT) devices. The proposed structures for analog arithmetic operations are smaller than the state-of-the-art complementary metal oxide semiconductor (CMOS) counterparts by several orders of magnitude. Moreover, data to be processed and computing results can be locally stored, or the analog computing can be done in the nonvolatile SOT devices, which are exploited to experimentally implement the image edge detection and signal amplitude modulation with a simple structure. Furthermore, an artificial neural network (ANN) with SOT devices based synapses is constructed to realize pattern recognition with high accuracy of ≈95%.

New analysis and design of a RF rectifier for RFID and implantable devices.

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-µm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from -15 dBm to -4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitable to passive UHF RFID tag IC and implantable devices.

Effect of electrode-electrolyte spatial mismatch on transcranial direct current stimulation: a finite element modeling study.

OBJECTIVE: Despite the encouraging pilot results of transcranial direct current stimulation (tDCS) revealing its effectiveness in neuromodulation, there are also studies reporting inconsistent outcomes. Apart from previously studied factors, such as the differences in head model structures, anodal displacements, electrode shape and size, and connector position, the hypothesis that the inevitable spatial mismatch between the electrolyte buffer and electrode might shape current flow in the cerebral cortex was tested in this work, and our results potentially explain some of the reported inconsistent outcomes. APPROACH: A finite element head model was built using cylinder electrodes with an arbitrary diameter of 2 cm. Current flow induced by different spatial mismatch types, degrees, and directions was simulated for three montages targeting the left motor cortex. Voxel-level current density differences and Jaccard index values of different percentiles for each mismatched configuration were calculated and compared throughout the cerebral cortex to determine the effect of electrode-electrolyte geometric mismatch. MAIN RESULTS: Spatial mismatch between the electrolyte buffer and electrode affected the current density distribution in the cerebral cortex to different extents, depending on the position of the return electrode and mismatch type, degree, and direction. Single cortical voxel current-density variance induced by the 50% excess or insufficient mismatch was as high as 14.44% or 38.04%, respectively. Moreover, the distribution of variance changed directionally with the mismatch orientation. Compared with the insufficient mismatch and single-directional mismatch, the excessive and symmetrical mismatch caused a less obvious effect on the current density distribution of tDCS. Specifically, the symmetrical excess electrolyte caused around 2%-4% current density changes for all the montages, with different degrees and directions of mismatch. When the target position was fixed at C3, maximum sensitivity to the electrolyte-electrode mismatch was achieved with Iz as the return electrode, compared with the other two choices. Further, more than 20% voxels with >90% percentile of the peak current density values would shift position if >30% insufficient geometric mismatch occurred for montage C3-Iz. SIGNIFICANCE: Our findings suggest that special attention is required regarding the spatial matching of the electrolyte buffer to the electrode during tDCS to avoid unexpected large changes in current distribution.

Bioheat transfer model of transcutaneous spinal cord stimulation-induced temperature changes.

Transcutaneous spinal cord stimulation (tSCS) has been extensively studied due to its promising application in motor function restoration. Many previous studies have explored both the essential mechanism of action and the methods for determining optimal stimulation parameters. In contrast, the bioheat transfer analysis of tSCS therapy has not been investigated to the same extent, despite widely existing, and being of great significance in assuring a stable and thermally safe treatment. In this paper, we concentrated on the thermal effects of tSCS using a finite element-based method. By coupling the electric field and bioheat field, systematic finite element simulations were performed on a human spinal cord model to survey the influence of anatomical structures, blood perfusion, and stimulation parameters on temperature changes for the first time. The results show that tSCS-induced temperature rise mainly occurs in the skin and fat layers and varies due to individual differences. The current density distribution along with the interactions of multiple biothermal effects synthetically determines the thermal status of the whole spinal cord model. Smaller stimulation electrodes have a higher risk of thermal damage when compared with larger electrodes. Increasing the stimulation intensity will result in more joule heat accumulation, hence an increase in the temperature. Among all configurations in this study that simulated the clinical tSCS protocols, the temperature rise could reach up to 9.4 °C on the skin surface depending on the stimulation parameters and tissue blood perfusion.