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Atomically two-dimensional (2D) materials have generated widespread interest for novel electronics and optoelectronics. Specially, owing to atomically thin 2D structure, the electronic bandgap of 2D semiconductors can be engineered by manipulating the surrounding dielectric environment. In this work, we develop an effective and controllable approach to manipulate dielectric properties of h-BN through gallium ions (Ga+) implantation for the first time. And the maximum surface potential difference between the intrinsic h-BN (h-BN) and the Ga+implanted h-BN (Ga+-h-BN) is up to 1.3 V, which is characterized by Kelvin probe force microscopy. More importantly, the MoTe2transistor stacked on Ga+-h-BN exhibits p-type dominated transfer characteristic, while the MoTe2transistor stacked on the intrinsic h-BN behaves as n-type, which enable to construct MoTe2heterojunction through dielectric engineering of h-BN. The dielectric engineering also provides good spatial selectivity and allows to build MoTe2heterojunction based on a single MoTe2flake. The developed MoTe2heterojunction shows stable anti-ambipolar behaviour. Furthermore, we preliminarily implemented a ternary inverter based on anti-ambipolar MoTe2heterojunction. Ga+implantation assisted dielectric engineering provides an effective and generic approach to modulate electric bandgap for a wide variety of 2D materials. And the implementation of ternary inverter based on anti-ambipolar transistor could lead to new energy-efficient logical circuit and system designs in semiconductors.
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The finite energy band-offset that appears between band structures of employed materials in a broken-gap heterojunction exhibits several interesting phenomena. Here, by employing a black phosphorus (BP)/rhenium disulfide (ReS2 ) heterojunction, the tunability of the BP work function (Φ BP ) with variation in flake thickness is exploited in order to demonstrate that a BP-based broken-gap heterojunction can manifest diverse current-transport characteristics such as gate tunable rectifying p-n junction diodes, Esaki diodes, backward-rectifying diodes, and nonrectifying devices as a consequence of diverse band-bending at the heterojunction. Diversity in band-bending near heterojunction is attributed to change in the Fermi level difference (Δ) between BP and ReS2 sides as a consequence of Φ BP modulation. No change in the current transport characteristics in several devices with fixed Δ also provides further evidence that current-transport is substantially impacted by band-bending at the heterojunction. Optoelectronic experiments on the Esaki diode and the p-n junction diode provide experimental evidence of band-bending diversity. Additionally, the p+ -n-p junction comprising BP (38 nm)/ReS2 /BP(5.8 nm) demonstrates multifunctionality of binary and ternary inverters as well as exhibiting the behavior of a bipolar junction transistor with common-emitter current gain up to 50.
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Multivalued logic circuits, which can handle more information than conventional binary logic circuits, have attracted much attention as a promising way to improve the data-processing capabilities of integrated circuits. In this study, we developed a ternary inverter based on organic field-effect transistors (OFET) as a potential component of high-performance and flexible integrated circuits. Key elements are anti-ambipolar and n-type OFETs connected in series. First, we demonstrate an organic ternary inverter that exhibits three distinct logic states. Second, the operating voltage was greatly reduced by taking advantage of an Al2O3 gate dielectric. Finally, the operating voltage was finely tuned by the designing of the device geometry. These results are achievable owing to the flexible controllability of the device configuration, suggesting that the organic ternary inverter plays an important role with regard to high-performance organic integrated circuits.
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In this paper, a novel transistor based on a hybrid conduction mechanism of band-to-band tunneling and drift-diffusion is proposed and investigated with the aid of TCAD tools. Besides the on and off states, the proposed device presents an additional intermediate state between the on and off states. Based on the tri-state behavior of the proposed TDFET (tunneling and drift-diffusion field-effect transistor), a ternary inverter is designed and its operation principle is studied in detail. It was found that this device achieves ternary logic with only two components, and its structure is simple. In addition, the influence of the supply voltage and the key device parameters are also investigated.
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Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (â¼3 × 103), wide NDT ranges (â¼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.
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Conventional transistors have long emphasized signal modulation and amplification, often sidelining polarity considerations. However, the recent emergence of negative differential transconductance, characterized by a drain current decline during gate voltage sweeping, has illuminated an unconventional path in transistor technology. This phenomenon promises to simplify the implementation of ternary logic circuits and enhance energy efficiency, especially in multivalued logic applications. Our research has culminated in the development of a sophisticated mixed transconductance transistor (M-T device) founded on a precise Te and IGZO heterojunction. The M-T device exhibits a sequence of intriguing phenomena, zero differential transconductance (ZDT), positive differential transconductance (PDT), and negative differential transconductance (NDT) contingent on applied gate voltage. We clarify its operation using a three-segment equivalent circuit model and validate its viability with IGZO TFT, Te TFT, and Te/IGZO TFT components. In a concluding demonstration, the M-T device interconnected with Te TFT achieves a ternary inverter with an intermediate logic state. Remarkably, this configuration seamlessly transitions into a binary inverter when it is exposed to light.
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Circuits based on organic electrochemical transistors (OECTs) have great potential in the fields of biosensors and artificial neural computation due to their biocompatibility and neural similarity. However, the integration of OECT-based circuits lags far behind other emerging electronics. Here, ternary inverters based on antiambipolar vertical OECTs (vOECTs) and their integration with the establishment of neural networks are demonstrated. Specifically, by adopting a small molecule (t-gdiPDI) as the channel of vOECT, high antiambipolar performance, with current density of 33.9 ± 2.1 A cm-2 under drain voltage of 0.1 V, peak voltage ≈0 V, low driving voltage < ± 0.6 V, and current on/off ratio > 106, are realized. Consequently, vertically stacked ternary circuits based solely on OECTs are constructed for the first time, showing three distinct logical states and high integration density. By further developing inverter array as the internal fundamental units of ternary weight network hardware circuits for ternary processing and computation, it demonstrates excellent data classification and recognition capabilities. This work demonstrates the possibility of constructing multi-valued logic circuits by OECTs and promotes a new strategy for high-density integration and multivalued computing systems based on organic circuits.
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In this article, we propose a dual-gate dielectric face tunnel field-effect transistor (DGDFTFET) that can exhibit three different output voltage states. Meanwhile, according to the requirements of the ternary operation in the ternary inverter, four related indicators representing the performance of the DGDFTFET are proposed, and we explain the impact of these indicators on the inverter and confirm that better indicators can be obtained by choosing appropriate design parameters for the device. Then, the ternary inverter implemented with this device can exhibit voltage transfer characteristics (VTCs) with three stable output voltage levels and bigger static noise margins (SNMs). In addition, by comparing the indicators of the DGDFTFET and a face tunnel field-effect transistor (FTFET), as well as the SNM of inverters, it is demonstrated that the performance of the DGDFTFET far surpasses the FTFET.
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The electrical and optical characteristics of two-dimensional (2D) transition-metal dichalcogenides (TMDCs) can be improved by surface modification. In this study, distinctive field-effect transistors (FETs) were realized by forming cross-type 2D WSe2/MoS2 p-n heterojunctions through surface treatment using poly(methyl methacrylate-co-methacrylic acid) (PMMA-co-PMAA). The FETs were applied to new ternary inverters as multivalued logic circuits (MVLCs). Laser confocal microscope photoluminescence spectroscopy indicated the generation of trions in the WSe2 and MoS2 layers, and the intensity decreased after PMMA-co-PMAA treatment. For the cross-type WSe2/MoS2 p-n heterojunction FETs subjected to PMMA-co-PMAA treatment, the channel current and the region of anti-ambipolar transistor characteristics increased considerably, and ternary inverter characteristics with three stable logic states, "1", "1/2", and "0", were realized. Interestingly, the intermediate logic state 1/2, which results from the negative differential transconductance characteristics, was realized by the turn-on of all component FETs, as the current of the FETs increased after PMMA-co-PMAA treatment. The electron-rich carboxyl acid moieties in PMMA-co-PMAA can undergo coordination with the metal Mo or W atoms present in the Se or S vacancies, respectively, resulting in the modulation of charge density. These features yielded distinctive FETs and ternary inverters for MVLCs using cross-type WSe2/MoS2 heterojunctions.
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Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H-TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H-TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (VOUT ) does not fully swing from VDD to GND . A new H-TR device structure that consists of a dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) layer stacked on a PTCDI-C13 layer is presented. Due to the continuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p-type off/p-type subthreshold region /NTC/ p-type on. As a result, it has a very high on/off current ratio (≈105 ) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H-TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full VDD -to-GND swing of VOUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis-free operation due to the use of a hydrophobic gate dielectric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time.
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We investigate the electric transport in a graphene-organic dye hybrid and the formation of p-n junctions. In the conventional approach, graphene p-n junctions are produced by using multiple electrostatic gates or local chemical doping, which produce different types of carriers in graphene. Instead of using multiple gates or typical chemical doping, a different approach to fabricate p-n junctions is proposed. The approach is based on optical gating of photosensitive dye molecules; this method can produce a well-defined sharp junction. The potential difference in the proposed p-n junction can be controlled by varying the optical power of incident light. A theoretical calculation based on the effective medium theory is performed to thoroughly explain the experimental data. The characteristic transport behavior of the photosensitive graphene p-n junction opens new possibilities for graphene-based devices, and we use the results to fabricate ternary inverters. Our strategy of building a simple hybrid p-n junction can further offer many opportunities in the near future of tuning it for other optoelectronic functionalities.
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Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metal-oxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (VTHs). Here, we report a finding: the photoinduced drain current in graphene/WSe2 heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the light-induced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe2 junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe2-based MVL logic circuits by using the ID-VG characteristics with two distinctive VTHs. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔVout of each state <0.05 V). Our study offers the pathway to substantialize MVL systems.