Detecting defects that reduce breakdown voltage using machine learning and optical profilometry.

Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary.

Using machine learning with optical profilometry for GaN wafer screening.

To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques-including optical profilometry-produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70-75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.

Optimizing performance and yield of vertical GaN diodes using wafer scale optical techniques.

To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm2, which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (Ron). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.

Steady-state methods for measuring in-plane thermal conductivity of thin films for heat spreading applications.

The development of high thermal conductivity thin film materials for the thermal management of electronics requires accurate and precise methods for characterizing heat spreading capability, namely, in-plane thermal conductivity. However, due to the complex nature of thin film thermal property measurements, resolving the in-plane thermal conductivity of high thermal conductivity anisotropic thin films with high accuracy is particularly challenging. Capable transient techniques exist; however, they usually measure thermal diffusivity and require heat capacity and density to deduce thermal conductivity. Here, we present an explicit uncertainty analysis framework for accurately resolving in-plane thermal conductivity via two independent steady-state thermometry techniques: particle-assisted Raman thermometry and electrical resistance thermometry. Additionally, we establish error-based criteria to determine the limiting experimental conditions that permit the simplifying assumption of one-dimensional thermal conduction to further reduce thermal analysis. We demonstrate the accuracy and precision (<5% uncertainty) of both steady-state techniques through in-plane thermal conductivity measurements of anisotropic nanocrystalline diamond thin films.

Experimental observation of localized interfacial phonon modes.

Interfaces impede heat flow in micro/nanostructured systems. Conventional theories for interfacial thermal transport were derived based on bulk phonon properties of the materials making up the interface without explicitly considering the atomistic interfacial details, which are found critical to correctly describing thermal boundary conductance. Recent theoretical studies predicted the existence of localized phonon modes at the interface which can play an important role in understanding interfacial thermal transport. However, experimental validation is still lacking. Through a combination of Raman spectroscopy and high-energy-resolution electron energy-loss spectroscopy in a scanning transmission electron microscope, we report the experimental observation of localized interfacial phonon modes at ~12 THz at a high-quality epitaxial Si-Ge interface. These modes are further confirmed using molecular dynamics simulations with a high-fidelity neural network interatomic potential, which also yield thermal boundary conductance agreeing well with that measured in time-domain thermoreflectance experiments. Simulations find that the interfacial phonon modes have an obvious contribution to the total thermal boundary conductance. Our findings significantly contribute to the understanding of interfacial thermal transport physics and have impact on engineering thermal boundary conductance at interfaces in applications such as electronics thermal management and thermoelectric energy conversion.

Room Temperature Skyrmions in Strain-Engineered FeGe thin films.

Skyrmions hold great promise for low-energy consumption and stable high density information storage, and stabilization of the skyrmion lattice (SkX) phase at or above room temperature is greatly desired for practical use. The topological Hall effect can be used to identify candidate systems above room temperature, a challenging regime for direct observation by Lorentz electron microscopy. Atomically ordered FeGe thin films are grown epitaxially on Ge(111) substrates with ~ 4 % tensile strain. Magnetic characterization reveals enhancement of Curie temperature to 350 K due to strain, well above the bulk value of 278 K. Strong topological Hall effect was observed between 10 K and 330 K, with a significant increase in magnitude observed at 330 K. The increase in magnitude occurs just below the Curie temperature, a similar relative temperature position as the onset of Skx phase in bulk FeGe. The results suggest that strained FeGe films may host a SkX phase above room temperature when significant tensile strain is applied.

Tunable Thermal Energy Transport across Diamond Membranes and Diamond-Si Interfaces by Nanoscale Graphoepitaxy.

The development of electronic devices, especially those that involve heterogeneous integration of materials, has led to increased challenges in addressing their thermal operational temperature demands. The heat flow in these systems is significantly influenced or even dominated by thermal boundary resistance at the interface between dissimilar materials. However, controlling and tuning heat transport across an interface and in the adjacent materials has so far drawn limited attention. In this work, we grow chemical vapor-deposited diamond on silicon substrates by graphoepitaxy and experimentally demonstrate tunable thermal transport across diamond membranes and diamond-silicon interfaces. We observed the highest diamond-silicon thermal boundary conductance (TBC) measured to date and increased diamond thermal conductivity due to strong grain texturing in the diamond near the interface. Additionally, nonequilibrium molecular dynamics simulations and a Landauer approach are used to understand the diamond-silicon TBC. These findings pave the way for tuning or increasing thermal conductance in heterogeneously integrated electronics that involve polycrystalline materials and will impact applications including electronics thermal management and diamond growth.

Technique for the dry transfer of epitaxial graphene onto arbitrary substrates.

To make graphene technologically viable, the transfer of graphene films to substrates appropriate for specific applications is required. We demonstrate the dry transfer of epitaxial graphene (EG) from the C-face of 4H-SiC onto SiO(2), GaN and Al(2)O(3) substrates using a thermal release tape. Subsequent Hall effect measurements illustrated that minimal degradation in the carrier mobility was induced following the transfer process in lithographically patterned devices. Correspondingly, a large drop in the carrier concentration was observed following the transfer process, supporting the notion that a gradient in the carrier density is present in C-face EG, with lower values being observed in layers further removed from the SiC interface. X-ray photoemission spectra collected from EG films attached to the transfer tape revealed the presence of atomic Si within the EG layers, which may indicate the identity of the unknown intrinsic dopant in EG. Finally, this transfer process is shown to enable EG films amenable for use in device fabrication on arbitrary substrates and films that are deemed most beneficial to carrier transport, as flexible electronic devices or optically transparent contacts.