Ultrathin VSe2 Nanosheets with Fast Ion Diffusion and Robust Structural Stability for Rechargeable Zinc-Ion Battery Cathode.

The realizing of high-performance rechargeable aqueous zinc-ion batteries (ZIBs) with high energy density and long cycling life is promising but still challenging due to the lack of suitable layered cathode materials. The work reports the excellent zinc-ion storage performance as-observed in few-layered ultrathin VSe2 nanosheets with a two-step Zn2+ intercalation/de-intercalation mechanism verified by ex situ X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) characterizations. The VSe2 nanosheets exhibit a discharge plateau at 1.0-0.7 V, a specific capacity of 131.8 mAh g-1 (at 0.1 A g-1 ), and a high energy density of 107.3 Wh kg-1 (at a power density of 81.2 W kg-1 ). More importantly, outstanding cycle stability (capacity retention of 80.8% after 500 cycles) without any activation process is achieved. Such a prominent cyclic stability should be attributed to its fast Zn2+ diffusion kinetics (DZn 2+  ≈ 10-8 cm-2 s-1 ) and robust structural/crystalline stability. Density functional theory (DFT) calculation further reveals a strong metallic characteristic and optimal zinc-ion diffusion pathway with a hopping energy barrier of 0.91 eV. The present finding implies that 2D ultrathin VSe2 is a very promising cathode material in ZIBs with remarkable battery performance superior to other layered transitional metal dichalcogenides.

Delamination of Plasticized Devices in Dynamic Service Environments.

With the continuous development of advanced packaging technology in heterogeneous semiconductor integration, the delamination failure problem in a dynamic service environment has gradually become a key factor limiting the reliability of packaging devices. In this paper, the delamination failure mechanism of polymer-based packaging devices is clarified by summarizing the relevant literature and the latest research solutions are proposed. The results show that, at the microscopic scale, thermal stress and moisture damage are still the two main mechanisms of two-phase interface failure of encapsulation devices. Additionally, the application of emerging technologies such as RDL structure modification and self-healing polymers can significantly improve the thermal stress state of encapsulation devices and enhance their moisture resistance, which can improve the anti-delamination reliability of polymer-based encapsulation devices. In addition, this paper provides theoretical support for subsequent research and optimization of polymer-based packages by summarizing the microscopic failure mechanism of delamination at the two-phase interface and introducing the latest solutions.

Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling.

As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts a thermo-mechanical analysis of TSV structures within multi-layered complex interposers, and analyzes the thermal stress behavior and reliability under variable temperature conditions (-55 °C to 85 °C), taking into account the typical electroplating defects within the copper pillars in TSVs. Initially, an overall model is established to determine the critical TSV locations. Sub-model analysis is then employed to investigate the stress and deformation of the most critical TSV, enabling the calculation of the temperature cycle life accordingly. Results indicate that the most critical TSV resides centrally within the model, exhibiting the highest equivalent stress. During the temperature cycling process, the maximum deformation experiences approximately periodic variations, while the maximum equivalent stress undergoes continuous accumulation and gradually diminishes. Its peak occurs at the contact interface corner between the TSV and Redistribution Layer (RDL). The estimated life of the critical point is 3.1708 × 105 cycles. Furthermore, it is observed that electroplating defect b alleviates thermal stress within TSVs during temperature cycling. This study provides insights into TSV thermal behavior and reliability, which are crucial for optimizing the design and manufacturing processes of advanced semiconductor packaging.

Progress in Research on Co-Packaged Optics.

In the 5G era, the demand for high-bandwidth computing, transmission, and storage has led to the development of optoelectronic interconnect technology. This technology has evolved from traditional board-edge optical modules to smaller and more integrated solutions. Co-packaged optics (CPO) has evolved as a solution to meet the growing demand for data. Compared to typical optoelectronic connectivity technology, CPO presents distinct benefits in terms of bandwidth, size, weight, and power consumption. This study presents an overview of CPO, highlighting its fundamental principles, advantages, and distinctive features. Additionally, it examines the current research progress of two distinct approaches utilizing Vertical-Cavity Surface-Emitting Laser (VCSEL) and silicon photonics integration technology. Additionally, it provides a concise overview of the many application situations of CPO. Expanding on this, the analysis focuses on the CPO using 2D, 2.5D, and 3D packaging techniques. Lastly, taking into account the present technological environment, the scientific obstacles encountered by CPO are analyzed, and its future progress is predicted.

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review.

With the advancement of Moore's Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device's failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging.

Residual Stress and Warping Analysis of the Nano-Silver Pressureless Sintering Process in SiC Power Device Packaging.

Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin-lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal stress analysis of the nano-silver pressureless sintering process is more limited. In this study, the pressureless sintering process of nano-silver was studied using finite element software, with nano-silver as an interconnect material. Using the control variable method, we analyzed the influences of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices. In addition, orthogonal experiments were designed to optimize the parameters and determine the optimal combination of the process parameters. The results showed that the maximum residual stress of the module appeared on the connection surface between the power chip and the nano-silver solder paste layer. The module warping deformation was convex warping. The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wave change. Each parameter influenced the stress of the solder layer in this descending order: sintering temperature, cooling rate, solder paste area, and solder paste thickness. The residual stress of the nano-silver layer was 24.83 MPa under the optimal combination of the process parameters and was reduced by 29.38% compared with the original value of 35.162 MPa.

Study on Single Event Effects of Enhanced GaN HEMT Devices under Various Conditions.

GaN HEMT devices are sensitive to the single event effect (SEE) caused by heavy ions, and their reliability affects the safe use of space equipment. In this work, a Ge ion (LET = 37 MeV·cm2/mg) and Bi ion (LET = 98 MeV·cm2/mg) were used to irradiate Cascode GaN power devices by heavy ion accelerator experimental device. The differences of SEE under three conditions: pre-applied electrical stress, different LET values, and gate voltages are studied, and the related damage mechanism is discussed. The experimental results show that the pre-application of electrical stress before radiation leads to an electron de-trapping effect, generating defects within the GaN device. These defects will assist in charge collection so that the drain leakage current of the device will be enhanced. The higher the LET value, the more electron-hole pairs are ionized. Therefore, the charge collected by the drain increases, and the burn-out voltage advances. In the off state, the more negative the gate voltage, the higher the drain voltage of the GaN HEMT device, and the more serious the back-channel effect. This study provides an important theoretical basis for the reliability of GaN power devices in radiation environments.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

The Study of the Reliability of Complex Components during the Electromigration Process.

With the increasing number of inputs and outputs, and the decreasing interconnection spacing, electrical interconnection failures caused by electromigration (EM) have attracted more and more attention. The electromigration reliability and failure mechanism of complex components were studied in this paper. The failure mechanism and reliability of complex components during the electromigration process were studied through the simulation and the experiment, which can overcome the limitation of experimental measurement at a micro-scale. The simulation results indicated that the solder joint has obvious current crowding at the current inlet, which will significantly enhance the electromigration effect. Based on the atomic flux divergence method, the void formation of solder joints can be effectively predicted, and life prediction can be more accurate than Black's equation. Experimental results indicated that the resistance of the daisy chain could be significantly increased with the process of void formation in the solder and corrosion of the leads. Moreover, the growth of intermetallic compounds can be obviously promoted under current stress. The main composition of the intermetallic compounds changes from almost entirely Cu5Sn6 to Cu5Sn6 and Cu3Sn; the cracks can be detected at the Cu3Sn layer. Specifically, the mean time to failure is 1065 h under 1.4 A current and 125 °C based on IPC-9701A guidelines.

Thermal Performance Optimization of Integrated Microchannel Cooling Plate for IGBT Power Module.

In high-integration electronic components, the insulated-gate bipolar transistor (IGBT) power module has a high working temperature, which requires reasonable thermal analysis and a cooling process to improve the reliability of the IGBT module. This paper presents an investigation into the heat dissipation of the integrated microchannel cooling plate in the silicon carbide IGBT power module and reports the impact of the BL series micropump on the efficiency of the cooling plate. The IGBT power module was first simplified as an equivalent-mass block with a mass of 62.64 g, a volume of 15.27 cm3, a density of 4.10 g/cm3, and a specific heat capacity of 512.53 J/(kg·K), through an equivalent method. Then, the thermal performance of the microchannel cooling plate with a main channel and a secondary channel was analyzed and the design of experiment (DOE) method was used to provide three factors and three levels of orthogonal simulation experiments. The three factors included microchannel width, number of secondary inlets, and inlet diameter. The results show that the microchannel cooling plate significantly reduces the temperature of IGBT chips and, as the microchannel width, number of secondary inlets, and inlet diameter increase, the junction temperature of chips gradually decreases. The optimal structure of the cooling plate is a microchannel width of 0.58 mm, 13 secondary inlets, and an inlet diameter of 3.8 mm, and the chip-junction temperature of this structure is decreased from 677 °C to 77.7 °C. In addition, the BL series micropump was connected to the inlet of the cooling plate and the thermal performance of the microchannel cooling plate with a micropump was analyzed. The micropump increases the frictional resistance of fluid flow, resulting in an increase in chip-junction temperature to 110 °C. This work demonstrates the impact of micropumps on the heat dissipation of cooling plates and provides a foundation for the design of cooling plates for IGBT power modules.

Temperature Cycle Reliability Analysis of an FBAR Filter-Bonded Ceramic Package.

On the background that the operating frequency of electronic devices tends to the radio frequency (RF) segment, a film bulk acoustic resonator (FBAR) filter is widely used in communication and military fields because of its advantages of high upper frequency, ample power capacity, small size, and low cost. However, the complex and harsh working environment puts higher requirements for packaging FBAR filters. Based on the Anand constitutive equation, the stress-strain response of the bonded ceramic package was studied by the finite element method for the FBAR filter-bonded ceramic package, and the thermal fatigue life of the device was predicted. We developed solder models with various spillage morphologies based on the random generation technique to examine the impact of spillage on device temperature reliability. The following are the primary conclusions: (1) Solder undergoes periodic deformation, stress, and strain changes throughout the cycle. (2) The corner of the contact surface between the chip and the solder layer has the largest stress at the end of the cycle, measuring 19.377 MPa. (3) The Engelmaier model predicts that the gadget will have a thermal fatigue life of 1928.67 h. (4) Expanding the layered solder area caused by any solder overflow mode may shorten the device's thermal fatigue life. The thermal fatigue life of a completely spilled solder is higher than that of a partially spilled solder.

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study.

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method.

In advanced packaging technology, the micro bump has become an important means of chip stacking and wafer interconnection. The reliability of micro bumps, which plays an important role in mechanical support, electrical connection, signal transmission and heat dissipation, determines the quality of chip packaging. Surface morphological defects are one of the main factors affecting the reliability of micro bumps, which are closely related to materials and bonding process parameters. In this paper, the electrodeposition process of preparing gold bumps is simulated at the atomic scale using the Kinetic Monte Carlo method. The differences in surface morphology and roughness of the plated layer are studied from a microscopic perspective under different deposition parameters. The results show that the gold micro bumps prepared by electrodeposition have better surface quality under conditions of lower deposition voltage, lower ion concentration and higher plating temperature, which can provide significant guidance for engineering applications.

Study on Cavitation, Warpage Deformation, and Moisture Diffusion of Sop-8 Devices during Molding Process.

Plastic packaging has shown its advantages over ceramic packaging and metal packaging in lightweight, thin, and high-density electronic devices. In this paper, the reliability and moisture diffusion of Sop-8 (Small Out-Line Package-8) plastic packaging devices are studied, and we put forward a set of complete optimization methods. Firstly, we propose to improve the reliability of plastic packaging devices by reducing the amount of cavitation and warpage deformation. Structural and process factors were investigated in the injection molding process. An orthogonal experiment design was used to create 25 groups of simulation experiments, and Moldflow software was used to simulate the flow mode analysis. Then, the simulation results are subjected to range analysis and comprehensive weighted score analysis. Finally, different optimization methods are proposed according to different production conditions, and each optimization method can reduce cavitation or warpage by more than 9%. The moisture diffusion of the Sop-8 plastic packing devices was also investigated at the same time. It was determined that the contact surface between the lead frame and the plastic packaging material was more likely to exhibit delamination under the condition of MSL2 moisture diffusion because the humidity gradient was easily produced at the crucial points of different materials. The diffusion of moisture is related to the type of plastic packaging material and the diffusion path.

Simulation of Single-Event Transient Effect for GaN High-Electron-Mobility Transistor.

A GaN high-electron-mobility transistor (HEMT) was simulated using the semiconductor simulation software Silvaco TCAD in this paper. By constructing a two-dimensional structure of GaN HEMT, combined with key models such as carrier mobility, the effects of a different state, different incidence position, different drain voltage, different LET values, and a different incidence angle on the single-event transient effect of GaN HEMT are simulated. LET stands for the linear energy transfer capacity of a particle, which refers to the amount of energy transferred by the particle to the irradiated substance on the unit path. The simulation results show that for GaN HEMTs, the single-event transient effect is more obvious when the device is in off-state than in on-state. The most sensitive location of GaN HEMTs to the single-event effect is in the region near the drain. The peak transient current increases with the increase in the drain bias and incident ion LET values. The drain charge collection time increases with the angle of incidence of heavy ion.

Effect of P-Type GaN Buried Layer on the Temperature of AlGaN/GaN HEMTs.

In this paper, a P-type GaN buried layer is introduced into the buffer layer of AlGaN/GaN HEMTs, and the effect of the P-type GaN buried layer on the device's temperature characteristics is studied using Silvaco TCAD software. The results show that, compared to the conventional device structure, the introduction of a P-type GaN buried layer greatly weakens the peak of the channel electric field between the gate and drain of the device. This leads to a more uniform electric field distribution, a substantial reduction in the lattice temperature of the device, and a more uniform temperature distribution. Therefore, the phenomenon of negative resistance caused by self-heating effect is significantly mitigated, while the breakdown performance of the device is also notably enhanced.

Defect Dipole Behaviors on the Strain Performances of Bismuth Sodium Titanate-Based Lead-Free Piezoceramics.

Bismuth sodium titanate (BNT)-based, lead-free piezoelectric materials have been extensively studied due to their excellent strain characteristics and environmental friendliness. In BNTs, the large strain (S) usually requires a relatively large electric field (E) excitation, resulting in a low inverse piezoelectric coefficient d33* (S/E). Moreover, the hysteresis and fatigue of strain in these materials have also been bottlenecks impeding the applications. The current common regulation method is chemical modification, which mainly focuses on forming a solid solution near the morphotropic phase boundary (MPB) by adjusting the phase transition temperature of the materials, such as BNT-BaTiO3, BNT-Bi0.5K0.5TiO3, etc., to obtain a large strain. Additionally, the strain regulation based on the defects introduced by the acceptor, donor, or equivalent dopant or the nonstoichiometry has proven effective, but its underlying mechanism is still ambiguous. In this paper, we review the generation of strain and then discuss it from the domain, volume, and boundary effect perspectives to understand the defect dipole behavior. The asymmetric effect caused by the coupling between defect dipole polarization and ferroelectric spontaneous polarization is expounded. Moreover, the defect effect on the conductive and fatigue properties of BNT-based solid solutions is described, which will affect the strain characteristics. The optimization approach is appropriately evaluated while there are still challenges in the full understanding of the defect dipoles and their strain output, in which further efforts are needed to achieve new breakthroughs in atomic-level insight.

[Di-2-ethylhexyl phthalate and its metabolite single-ethylhexyl phthalate affect TGF-beta 1 expression and telomerase activity in the testis of young male rats].

OBJECTIVE: To investigate the influences of di-2-ethylhexyl phthalate (DEHP) and its metabolite single-ethylhexyl phthalate (MEHP) on the expression of transforming growth factor-beta 1 (TGF-beta1) and telomerase activity in young male Wistar METHODS: Ninety-six 2-week-old male Wistar rats were equally randomized into a normal control (NC) group, a positive control (PC) group, and six experimental groups. Those of the NC group were intragastrically administered 0.9% normal saline at a dose of 0.2 ml per kg per d for 3 weeks, those in the PC group cyclophosphamide (CTX) at 100 mg per kg per d for 1 week, and those of the experimental groups DEHP and MEHP, respectively, at a low dose (100 mg per kg per d) for 3 weeks, a moderate dose (200 mg per kg per d) for 2 weeks, and a high dose (300 mg per kg per d) for 1 week. Then we observed the morphological changes of the testicular sperm and counted the sperm heads and their abnormity rate at different doses and times. We detected the expression of TGF-beta1 in the testis tissue using immunohistochemical SABC and RT-PCR, measured the area density, and determined telomerase activity by ELISA. RESULTS: Compared with the NC group, the experimental groups showed an obvious reduction in the total sperm count and number of sperm heads (P < 0.05) and a significant increase in the rate of teratosperm (P < 0.05), such as decapitated, hookless, and double-tailed sperm. And there were no significant differences between the high-dose short-term and low-dose long-term medication groups (P > 0.05). The expression of TGF-beta1 was low in the NC group, high in the PC group, and obviously increased in the membrane and cytoplasm of spermatogenic cells of the experimental groups. The area density and TGF-beta1 mRNA expression were 0.156 0 +/- 0.003 5 and 1.51 +/- 0.20 in the NC group, 0.534 0 +/- 0.003 1 and 8.43 +/- 1.75 in the PC group, 0.289 0 +/- 0.003 6 and 3.83 +/- 1.57 in the DEHP groups, and 0.284 0 +/- 0.003 1 and 3.51 +/- 1.41 in the MEHP groups. There were significant differences between the experimental and the other two groups (P < 0.01), but not between the high-dose short-term and low-dose long-term medication groups (P > 0.05). Telomerase activity was remarkably reduced in the experimental groups as compared with the NC group (P < 0.05), but with no significant difference between the high-dose short-term and low-dose long-term medication groups (P > 0.05). CONCLUSION: DEHP and its metabolite MEHP can evidently induce spermatogenic injury in young male rats, which may be associated with their induction of increased TGF-beta1 expression and decreased telomerase activity in the rat testis.

Effect of Surface Roughness on the Electrical Performances of CPW Transmission Lines Used in Future Ultra-High Frequency Applications.

The development of integrated circuits and packaging technology has led to smaller and smaller transmission line sizes and higher and higher operating frequencies up to nearly 100 GHz. However, the skinning depth of transmission lines due to eddy currents becomes smaller and smaller as the operating frequency of coplanar wave guide (CPW) transmission lines becomes higher and higher, while the reduction of device size makes the skinning depth consistent with the surface roughness of the device. In this paper, the concept of modified roughness coefficient was proposed based on the existing correlation factor. The concept of threshold modified roughness coefficient was proposed with a 20 dB reflection coefficient as the threshold value. The effect of surface roughness on transmission line transmission performance at frequencies above 100 GHz up to 1000 GHz was investigated. It was found that when the operating frequency of the signal was greater than the threshold roughness coefficient, the effect of surface roughness on the transmission line reflection coefficient should be considered. The modified roughness coefficient in this paper could quickly determine the effect of surface roughness on transmission line performance at different frequencies.

Molecular Dynamics Analysis of Graphene Nanoelectromechanical Resonators Based on Vacancy Defects.

Due to the limitation of graphene processing technology, the prepared graphene inevitably contains various defects. The defects will have a particular influence on the macroscopic characteristics of the graphene. In this paper, the defect-based graphene nanoresonators are studied. In this study, the resonant properties of graphene were investigated via molecular dynamic simulations. The effect of vacancy defects and hole defects at different positions, numbers, and concentrations on the resonance frequency of graphene nanoribbons was studied. The results indicated that single monatomic vacancy has no effect on graphene resonant frequency, and the concentration of the resonant frequency of graphene decreases almost linearly with the increase of single-atom vacancy concentration. When the vacancy concentration is 5%, the resonance frequency is reduced by 12.77% compared to the perfect graphene. Holes on the graphene cause the resonance frequency to decrease. As the circular hole defect is closer to the center of the graphene nanoribbon, not only does its resonant frequency increase, but the tuning range is also expanded accordingly. Under the external force of 10.715 nN, the resonant frequency of graphene reaches 429.57 GHz when the circular hole is located at the center of the graphene nanoribbon, which is 40 GHz lower than that of single vacancy defect graphene. When the circular hole is close to the fixed end of graphene, the resonant frequency is 379.62 GHz, which is 90 GHz lower than that of single vacancy graphene. When the hole defect is at the center of nanoribbon, the frequency tunable range of graphene reaches 120 GHz. The tunable frequency range of graphene is 100.12 GHz when the hole defect is near the fixed ends of the graphene nanoribbon. This work is of great significance for design and performance optimization of graphene-based nanoelectro-mechanical system (NEMS) resonators.