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1.
IEEE Trans Neural Netw ; 3(3): 404-13, 1992.
Artículo en Inglés | MEDLINE | ID: mdl-18276444

RESUMEN

The design of a scalable, fully connected 3-D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits is proposed. The system design uses a hardware-efficient combination of pulsewidth-modulating optoelectronic neurons and pulse-amplitude-modulating electronic synapses. Low-area, high-linear-dynamic-range analog synapse and neuron circuits are proposed. SPICE circuit simulations and an experimental demonstration of the free-space optical interconnection system are included.

2.
Appl Opt ; 37(2): 205-27, 1998 Jan 10.
Artículo en Inglés | MEDLINE | ID: mdl-18268578

RESUMEN

We model and compare on-chip (up to wafer scale) and off-chip(multichip module) high-speed electrical interconnections withfree-space optical interconnections in terms of speed performance andenergy requirements for digital transmission in large-scalesystems. For all technologies the interconnections are firstmodeled and optimized for minimum delay as functions of theinterconnection length for both one-to-one and fan-outconnections. Then energy requirements are derived as functions ofthe interconnection length. Free-space optical interconnectionsthat use multiple-quantum-well modulators or vertical-cavitysurface-emitting lasers as transmitters are shown to offer aspeed-energy product advantage as high as 30 over that of the electrical interconnection technologies.

3.
Appl Opt ; 34(32): 7621-38, 1995 Nov 10.
Artículo en Inglés | MEDLINE | ID: mdl-21060641

RESUMEN

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 × 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

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