Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High-Performance, Low-Power Flexible Ternary Logic Circuits.

Organic multi-valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H-TRs). To achieve high-performance organic ternary logic circuits, the range of NTC in H-TRs must be optimized in advance to ensure the well-defined intermediate logic state in ternary logic inverters (T-inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H-TRs is presented. Each thickness of p-/n-type semiconductor in H-TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain (S/D) electrode structure is newly developed for H-TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T-inverter exhibits full-swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T-inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8 V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T-inverter production.

Vertical Charge Transport and Negative Transconductance in Multilayer Molybdenum Disulfides.

Negative transconductance (NTC) devices have been heavily investigated for their potential in low power logical circuit, memory, oscillating, and high-speed switching applications. Previous NTC devices are largely attributed to two working mechanisms: quantum mechanical tunneling, and mobility degradation at high electrical field. Herein we report a systematic investigation of charge transport in multilayer two-dimensional semiconductors (2DSCs) with optimized van der Waals contact and for the first time demonstrate NTC and antibipolar characteristics in multilayer 2DSCs (such as MoS2, WSe2). By varying the measurement temperature, bias voltage, and body thickness, we found the NTC behavior can be attributed to a vertical potential barrier in the multilayer 2DSCs and the competing mechanisms between intralayer lateral transport and interlayer vertical transport, thus representing a new working mechanism for NTC operation. Importantly, this vertical potential barrier arises from inhomogeneous carrier distribution in 2DSC from the near-substrate region to the bulk region, which is in contrast to conventional semiconductors with homogeneous doping defined by bulk dopants. We further show that the unique NTC behavior can be explored for creating frequency doublers and phase shift keying circuits with only one transistor, greatly simplifying the circuit design compared to conventional technology.

Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor.

The integration of functional materials into electronic devices has become a key approach to extending Moore's law by increasing the functional density of electronic circuits. Here, we present a device technology based on ultrascaled ferroelectric, antiambipolar transistors (ferro-AAT) with robust negative transconductance, enabling a wide range of reconfigurable functionalities with applications in both the digital and analog domains. The device relies on the integration of a hafnia-based ferroelectric gate stack on a vertical nanowire tunnel field-effect transistor. Through intentional gate/source overlap and tunnel-junction engineering, we demonstrate enhanced antiambipolarity with a high negative transconductance that is reconfigurable using the nonvolatile remanent polarization of the ferroelectric. Experimental validation highlights the versatility of this ferro-AAT in two implementation scenarios: content addressable memory (CAM) for high-density data search and reconfigurable signal processing in analog circuits. As a single-transistor cell for CAMs, the ferro-AAT shows subpicojoule operation for one search with a compact footprint of ∼0.01 µm2. For single-transistor-based signal modulation, multistate reconfigurations and high power conversion (>95%) are achieved in the ferro-AAT, resulting in a significant reduction in the complexity of analog circuit design. Our results reveal that the distinctive device properties allow ferro-AATs to operate beyond conventional transistors with multiple reconfigurable functionalities, ultrascaled footprint, and low power consumption.

Asymmetric two-dimensional ferroelectric transistor with anti-ambipolar transport characteristics.

Two-dimensional (2D) ferroelectric transistors hold unique properties and positions, especially talking about low-power memories, in-memory computing, and multifunctional logic devices. To achieve better functions, appropriate design of new device structures and material combinations is necessary. We present an asymmetric 2D heterostructure integrating MoTe2, h-BN, and CuInP2S6 as a ferroelectric transistor, which exhibits an unusual property of anti-ambipolar transport characteristic under both positive and negative drain biases. Our results demonstrate that the anti-ambipolar behavior can be modulated by external electric field, achieving a peak-to-valley ratio up to 103. We also provide a comprehensive explanation for the occurrence and modulation of the anti-ambipolar peak based on a model describing linked lateral-and-vertical charge behaviors. Our findings provide insights for designing and constructing anti-ambipolar transistors and other 2D devices with significant potential for future applications.