Embedment of Multiple Transition Metal Impurities into WS2 Monolayer for Bandstructure Modulation.

Band structure by design in 2D layered semiconductors is highly desirable, with the goal to acquire the electronic properties of interest through the engineering of chemical composition, structure, defect, stacking, or doping. For atomically thin transition metal dichalcogenides, substitutional doping with more than one single type of transition metals is the task for which no feasible approach is proposed. Here, the growth of WS2 monolayer is shown codoped with multiple kinds of transition metal impurities via chemical vapor deposition controlled in a diffusion-limited mode. Multielement embedment of Cr, Fe, Nb, and Mo into the host lattice is exemplified. Abundant impurity states thus generate in the bandgap of the resultant WS2 and provide a robust switch of charging/discharging states upon sweep of an electric filed. A profound memory window exists in the transfer curves of doped WS2 field-effect transistors, forming the basis of binary states for robust nonvolatile memory. The doping technique presented in this work brings one step closer to the rational design of 2D semiconductors with desired electronic properties.

A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications.

Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu3 Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu3 Ge/Ge/Cu3 Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 105 and 103 for the hole and electron regimes at room temperature, respectively. Investigations of temperature-dependent transport properties and low-frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary-signal and data-storage functions, which greatly simplify circuit design compared with conventional technologies.

Atomically thin van der Waals tunnel field-effect transistors and its potential for applications.

Power dissipation is a crucial problem as the packing density of transistors increases in modern integrated circuits. Tunnel field-effect transistors (TFETs), which have high energy filtering provided by band-to-band tunneling (BTBT), have been proposed as an alternative electronics architecture to decrease the energy loss in bias operation and to achieve steep switching at room temperature. Very recently, the BTBT behavior has been demonstrated in van der Waals heterostructures by using unintentionally doped semiconductors. The reason of the BTBT formation is attributed to a significant band bending near the heterointerface, resulting in carrier accumulations. In this work, to investigate charge transport in type-III transistors, we adopted the same band-bending concept to fabricate van der Waals BP/MoS2 heterostructures. Through analyzing the temperature dependence of their electrical properties, we carefully ruled out the contribution of metal-semiconductor contact resistances and improved our understanding of carrier injection in 2D type-III transistors. The BP/MoS2 heterostructures showed both negative differential resistance and 1/f 2 current fluctuations, strongly demonstrating the BTBT operation. Finally, we also designed a TFET based on this heterostructure with an ionic liquid gate, and this TFET demonstrated an subthreshold slope can successfully surmount the thermal limit of 60 mV/decade. This work improves our understanding of charge transport in such layered heterostructures and helps to improve the energy efficiency of next-generation nanoscale electronics.

Intrinsic Carrier Transport of Phase-Pure Homologous 2D Organolead Halide Hybrid Perovskite Single Crystals.

This work reveals the intrinsic carrier transport behavior of 2D organolead halide perovskites based on phase-pure homologous (n = 1, 2, and 3) Ruddelsden-Popper perovskite (RPP) (BA)2 (MA)n -1 Pbn I3n+1 single crystals. The 2D perovskite field effect transistors with high-quality exfoliated 2D perovskite bulk crystals are fabricated, and characteristic output and transfer curves are measured from individual single-crystal flakes with various n values under different temperatures. Unipolar n-type transport dominated the electrical properties of all these 2D RPP single crystals. The transport behavior of the 2D organolead halide hybrid perovskites exhibits a strong dependence on the n value and the mobility substantially increases as the ratio of the number of inorganic perovskite slabs per organic spacer increases. By extracting the effect of contact resistances, the corrected mobility values for n = 1, 2, and 3 are 2 × 10-3 , 8.3 × 10-2 , and 1.25 cm2 V-1 s-1 at 77 K, respectively. Furthermore, by combining temperature-dependent electrical transport and optical measurements, it is found that the origin of the carrier mobility dependence on the phase transition for 2D organolead halide perovskites is very different from that of their 3D counterparts. Our findings offer insight into fundamental carrier transport behavior of 2D organic-inorganic hybrid perovskites based on phase-pure homologous single crystals.

Thickness-dependent interfacial Coulomb scattering in atomically thin field-effect transistors.

Two-dimensional semiconductors are structurally ideal channel materials for the ultimate atomic electronics after silicon era. A long-standing puzzle is the low carrier mobility (µ) in them as compared with corresponding bulk structures, which constitutes the main hurdle for realizing high-performance devices. To address this issue, we perform a combined experimental and theoretical study on atomically thin MoS2 field effect transistors with varying the number of MoS2 layers (NLs). Experimentally, an intimate µ-NL relation is observed with a 10-fold degradation in µ for extremely thinned monolayer channels. To accurately describe the carrier scattering process and shed light on the origin of the thinning-induced mobility degradation, a generalized Coulomb scattering model is developed with strictly considering device configurative conditions, that is, asymmetric dielectric environments and lopsided carrier distribution. We reveal that the carrier scattering from interfacial Coulomb impurities (e.g., chemical residues, gaseous adsorbates, and surface dangling bonds) is greatly intensified in extremely thinned channels, resulting from shortened interaction distance between impurities and carriers. Such a pronounced factor may surpass lattice phonons and serve as dominant scatterers. This understanding offers new insight into the thickness induced scattering intensity, highlights the critical role of surface quality in electrical transport, and would lead to rational performance improvement strategies for future atomic electronics.

Plasma-Driven Selenization for Electrical Property Enhancement in Janus 2D Materials.

The recent emergence of Janus 2D materials like SnSSe, derived from SnS2, reveals unique electrical and optical features, such as asymmetrical electronic structure, enhanced carrier mobility, and tunable bandgap. Previous theoretical studies have discuss the electronic properties of Janus SnSSe, but experimental evidence is limited. This study presents a two-step method for synthesizing Janus SnSSe, involving hydrogen plasma treatment and in situ selenization. Optimized conditions (38 W, 1.5 min, 250 °C) are determined using Raman spectroscopy and AFM analysis. XPS confirmed SnSSe's elemental composition, while KPFM reveals a significant reduction in the work function (from 5.26 down to 5.14 eV) for the first time, indicating asymmetrically induced n-type doping. Finally, field-effect transistors (FETs) derived from SnSSe exhibited significantly enhanced mobility and on-current, as well as n-type doping, compared to SnS2-based FETs. These findings lay a crucial foundation for developing high-performance 2D electronic and optoelectronic devices.

Ultrafast and Broad-Band Graphene Heterojunction Photodetectors with High Gain.

Graphene possesses an exotic band structure that spans a wide range of important technological wavelength regimes for photodetection, all within a single material. Conventional methods aimed at enhancing detection efficiency often suffer from an extended response time when the light is switched off. The task of achieving ultrafast broad-band photodetection with a high gain remains challenging. Here, we propose a devised architecture that combines graphene with a photosensitizer composed of an alternating strip superstructure of WS2-WSe2. Upon illumination, n+-WS2 and p+-WSe2 strips create alternating electron- and hole-conduction channels in graphene, effectively overcoming the tradeoff between the responsivity and switch time. This configuration allows for achieving a responsivity of 1.7 × 107 mA/W, with an extrinsic response time of 3-4 µs. The inclusion of the superstructure booster enables photodetection across a wide range from the near-ultraviolet to mid-infrared regime and offers a distinctive photogating route for high responsivity and fast temporal response in the pursuit of broad-band detection.

Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design.

Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthreshold swing (80 mV dec-1) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of nonvolatile reconfigurability (a trap level of 1013 cm-2 eV-1). Furthermore, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at Vdd = 0.5 V) logic gates. This work provides an innovative 3D heterointegration prototype for future computing-in-memory hardware.

Single-Gate In-Transistor Readout of Current Superposition and Collapse Utilizing Quantum Tunneling and Ferroelectric Switching.

In nanostructure assemblies, the superposition of current paths forms microscopic electric circuits, and different circuit networks produce varying results, particularly when utilized as transistor channels for computing applications. However, the intricate nature of assembly networks and the winding paths of commensurate currents hinder standard circuit modeling. Inspired by the quantum collapse of superposition states for information decoding in quantum circuits, the implementation of analogous current path collapse to facilitate the detection of microscopic circuits by modifying their network topology is explored. Here, the superposition and collapse of current paths in gate-all-around polysilicon nanosheet arrays are demonstrated to enrich the computational resources within transistors by engineering the channel length and quantity. Switching the ferroelectric polarization of Hf0.5 Zr0.5 O2 gate dielectric, which drives these transistors out-of-equilibrium, decodes the output polymorphism through circuit topological modifications. Furthermore, a protocol for the single-electron readout of ferroelectric polarization is presented with tailoring the channel coherence. The introduction of lateral path superposition results into intriguing metal-to-insulator transitions due to transient behavior of ferroelectric switching. This ability to adjust the current networks within transistors and their interaction with ferroelectric polarization in polycrystalline nanostructures lays the groundwork for generating diverse current characteristics as potential physical databases for optimization-based computing.

Enhanced IL-10 production by CD4+ T cells primed in IL-15Rα-deficient mice.

In this study, we investigated the functional outcomes of CD4(+) T cells primed in the absence of IL-15 transpresentation. Compared with their WT counterparts primed in WT mice, IL-15Rα KO CD4(+) T cells primed in KO mice were found to exclusively overproduce IL-10 upon in vitro restimulation(.) The comparable expression of IL-4 and Foxp3 in CD4(+) T cells primed in the WT and IL-15Rα KO mice indicated that this was neither due to T(H) 2- nor Treg cell-differentiation. IL-10 overproduction was also observed when OVA-specific TCR transgenic CD4(+) T (OT-II) cells were primed in KO mice, excluding an intrinsic deficiency of KO CD4(+) T cells. To investigate the WT and KO microenvironment, DCs from both WT and IL-15Rα KO mice were compared. DCs from both backgrounds were indistinguishable in their steady-state survival and in their expression of MHC class II and costimulatory molecules CD80, CD86, and CD40. However, IL-15Rα KO DCs primed OT-II cells in vitro to produce higher levels of IL-10 upon their restimulation. Additionally, IL-15Rα KO DCs produced significantly more IL-10 upon activation, and IL-10 neutralization during DC-mediated in vitro priming abolished IL-10 overproduction by CD4(+) T cells. Thus, IL-15Rα KO DCs provide an IL-10-enriched environment that preferentially primes CD4(+) T cells for more IL-10 production, highlighting a regulatory role for IL-15 transpresentation in CD4(+) T-cell priming.

Dielectrophoretic placement of quasi-zero-, one-, and two-dimensional nanomaterials into nanogap for electrical characterizations.

DEP is one of promising techniques for positioning nanomaterials into the desirable location for nanoelectronic applications. In contrast, the lithography technique is commonly used to make ultra-thin conducting wires and narrow gaps but, due to the limit of patterning resolution, it is not feasible to make electrical contacts on ultra-small nanomaterials for a bottom-up device fabrication. Thus, integrating the lithography and dielectrophoresis, a real bottom-up fabrication can be achieved. In this work, the device with the nanogap in between two nanofinger-electrodes is made using electron-beam lithography from top down and the ultra-small nanomaterials, such as colloidal PbSe quantum dots, polyaniline nanofibers, and reduced-graphene-oxide flakes, are placed in the nanogap by DEP from bottom up. The threshold electric field for the DEP placement of PbSe nanocrystals was roughly estimated to be about 8.3 × 10(4) V/cm under our experimental configuration. After the DEP process, several procedures for reducing contact resistances are attempted and measurements of intrinsic electron transport in versatile nanomaterials are performed. It is experimentally confirmed that electron transport in both PbSe nanocrystal arrays and polyaniline nanofibers agrees well with Prof. Ping Sheng's model of granular metallic conduction. In addition, electron transport in reduced-graphene-oxide flakes follows Mott's 2D variable-range-hopping model. This study illustrates an integration of the electron-beam lithography and the DEP techniques for a precise manipulation of nanomaterials into electronic circuits for characterization of intrinsic properties.

WSe2/WS2 Heterobilayer Nonvolatile Memory Device with Boosted Charge Retention.

A two-dimensional (2D) nonvolatile memory device architecture to improve the long-term charge retention with the minimum charge loss without compromising storage capacity and the extinction ratio for practical applications has been an imminent demand. To address the current issue, we adopted a novel type-II band-aligned heterobilayer channel comprising vertically stacked monolayer WSe2 nanodots on monolayer WS2. The band offset modulation leads to electron doping from WSe2 nanodots into the WS2 channel without any external driving electric field. As a result, the tested device outperformed with a memory window as high as 34 V and a negligible charge loss of 7% in a retention period of 10 years while maintaining a high extinction ratio of 106. The doping technique presented in this work provides a feasible route to modulate the electrical properties of 2D channel materials without hampering charge transport, paving the way for high-performance 2D memory devices.

Filling the gap between topological insulator nanomaterials and triboelectric nanogenerators.

Reliable energy modules and higher-sensitivity, higher-density, lower-powered sensing systems are constantly required to develop wearable electronics and the Internet of Things technology. As an emerging technology, triboelectric nanogenerators have been potentially guiding the landscape of sustainable power units and energy-efficient sensors. However, the existing triboelectric series is primarily populated by polymers and rubbers, limiting triboelectric sensing plasticity to some extent owing to their stiff surface electronic structures. To enrich the current triboelectric group, we explore the triboelectric properties of the topological insulator nanofilm by Kelvin probe force microscopy and reveal its relatively positive electrification charging performance. Both the larger surface potential difference and the conductive surface states of the nanofilms synergistically improve the charge transfer behavior between the selected triboelectric media, endowing the topological insulator-based triboelectric nanogenerator with considerable output performance. Besides serving as a wearable power source, the ultra-compact device array demonstrates innovative system-level sensing capabilities, including precise monitoring of dynamic objects and real-time signal control at the human-machine interface. This work fills the blank between topological quantum matters and triboelectric nanogenerators and, more importantly, exploits the significant potential of topological insulator nanofilms for self-powered flexible/wearable electronics and scalable sensing technologies.

Reversible Charge-Polarity Control for Multioperation-Mode Transistors Based on van der Waals Heterostructures.

Van der Waals (vdW) heterostructures-in which layered materials are purposely selected to assemble with each other-allow unusual properties and different phenomena to be combined and multifunctional electronics to be created, opening a new chapter for the spread of internet-of-things applications. Here, an O2 -ultrasensitive MoTe2 material and an O2 -insensitive SnS2 material are integrated to form a vdW heterostructure, allowing the realization of charge-polarity control for multioperation-mode transistors through a simple and effective rapid thermal annealing strategy under dry-air and vacuum conditions. The charge-polarity control (i.e., doping and de-doping processes), which arises owing to the interaction between O2 adsorption/desorption and tellurium defects at the MoTe2 surface, means that the MoTe2 /SnS2 heterostructure transistors can reversibly change between unipolar, ambipolar, and anti-ambipolar transfer characteristics. Based on the dynamic control of the charge-polarity properties, an inverter, output polarity controllable amplifier, p-n diode, and ternary-state logics (NMIN and NMAX gates) are demonstrated, which inspire the development of reversibly multifunctional devices and indicates the potential of 2D materials.

Diffused Beam Energy to Dope van der Waals Electronics and Boost Their Contact Barrier Lowering.

Contact engineering of two-dimensional semiconductors is a central issue for performance improvement of micro-/nanodevices based on these materials. Unfortunately, the various methods proposed to improve the Schottky barrier height normally require the use of high temperatures, chemical dopants, or complex processes. This work demonstrates that diffused electron beam energy (DEBE) treatment can simultaneously reduce the Schottky barrier height and enable the direct writing of electrical circuitry on van der Waals semiconductors. The electron beam energy projected into the region outside the electrode diffuses into the main channel, producing selective-area n-type doping in a layered MoTe2 (or MoS2) field-effect transistor. As a result, the Schottky barrier height at the interface between the electrode and the DEBE-treated MoTe2 channel is as low as 12 meV. Additionally, because selective-area doping is possible, DEBE can allow the formation of both n- and p-type doped channels within the same atomic plane, which enables the creation of a nonvolatile and homogeneous MoTe2 p-n rectifier with an ideality factor of 1.1 and a rectification ratio of 1.3 × 103. These results indicate that the DEBE method is a simple, efficient, mask-free, and chemical dopant-free approach to selective-area doping for the development of van der Waals electronics with excellent device performances.

High-Quality Single-Crystalline ß-Ga2O3 Nanowires: Synthesis to Nonvolatile Memory Applications.

One of the promising nonvolatile memories of the next generation is resistive random-access memory (ReRAM). It has vast benefits in comparison to other emerging nonvolatile memories. Among different materials, dielectric films have been extensively studied by the scientific research community as a nonvolatile switching material over several decades and have reported many advantages and downsides. However, less attention has been given to low-dimensional materials for resistive memory compared to dielectric films. Particularly, ß-Ga2O3 is one of the promising materials for high-power electronics and exhibits the resistive switching phenomenon. However, low-dimensional ß-Ga2O3 nanowires have not been explored in resistive memory applications, which hinders further developments. In this article, we studied the resistance switching phenomenon using controlled electron flow in the 1D nanowires and proposed possible resistive switching and electron conduction mechanisms. High-density ß-Ga2O3 1D-nanowires on Si (100) substrates were produced via the VLS growth technique using Au nanoparticles as a catalyst. Structural characteristics were analyzed via SEM, TEM, and XRD. Besides, EDS, CL, and XPS binding feature analyses confirmed the composition of individual elements, the possible intermediate absorption sites in the bandgap, and the bonding characteristics, along with the presence of various oxygen species, which is crucial for the ReRAM performances. The forming-free bipolar resistance switching of a single ß-Ga2O3 nanowire ReRAM device and performance are discussed in detail. The switching mechanism based on the formation and annihilation of conductive filaments through the oxygen vacancies is proposed, and the possible electron conduction mechanisms in HRS and LRS states are discussed.

Electron transport in high-resistance semiconductor nanowires through two-probe measurements.

Since the successful fabrication of semiconductor nanowires, various techniques have been developed to contact these nanowires and to probe their intrinsic electrical properties. Although many novel quasi one-dimensional materials such as Pb(1 - x)Mn(x)Se nanoarrays were recently produced, their intrinsic electron transport properties have not been extensively studied so far. In this work, we demonstrate that an ordinary source-drain configuration of field-effect transistors or the two-probe measurement can be applied to the exploration of the intrinsic properties of nanowires. This two-probe measurement approach also works on highly resistive nanowires without an Ohmic contact issue. By using this method, electron transport behavior, resistivity, and carrier concentrations of ZnO, InP, GaP, and Pb(1 - x)Mn(x)Se semiconductor nanowires have been investigated. Due to the tiny cross-section and few conducting channels, a nanomaterial usually reveals an ultra high resistance. This technique demonstrates a two-probe characterization of nanostructures, paving the simplest way toward electrical characterizations of all high-resistance nanomaterials such as deoxyribonucleic acid (DNA), molecules and organics.

Facile and Reversible Carrier-Type Manipulation of Layered MoTe2 Toward Long-Term Stable Electronics.

Flexible manipulation of the carrier transport behaviors in two-dimensional materials determines their values of practical application in logic circuits. Here, we demonstrated the carrier-type manipulation in field-effect transistors (FETs) containing α-phase molybdenum ditelluride (MoTe2) by a rapid thermal annealing (RTA) process in dry air for hole-dominated and electron-beam (EB) treatment for electron-dominated FETs. EB treatment induced a distinct shift of the transfer curve by around 135 V compared with that of the FET-processed RTA treatment, indicating that the carrier density of the EB-treated FET was enhanced by about 1 order of magnitude. X-ray photoelectron spectroscopy analysis revealed that the atomic ratio of Te decreased from 66.4 to 60.8% in the MoTe2 channel after EB treatment. The Fermi level is pinned near the new energy level resulting from the Te vacancies produced by the EB process, leading to the electron-dominant effect of the MoTe2 FET. The electron-dominated MoTe2 FET showed excellent stability for more than 700 days. Thus, we not only realized the reversible modulation of carrier-type in layered MoTe2 FETs but also demonstrated MoTe2 channels with desirable performance, including long-term stability.

Oxidation-boosted charge trapping in ultra-sensitive van der Waals materials for artificial synaptic features.

Exploitation of the oxidation behaviour in an environmentally sensitive semiconductor is significant to modulate its electronic properties and develop unique applications. Here, we demonstrate a native oxidation-inspired InSe field-effect transistor as an artificial synapse in device level that benefits from the boosted charge trapping under ambient conditions. A thin InOx layer is confirmed under the InSe channel, which can serve as an effective charge trapping layer for information storage. The dynamic characteristic measurement is further performed to reveal the corresponding uniform charge trapping and releasing process, which coincides with its surface-effect-governed carrier fluctuations. As a result, the oxide-decorated InSe device exhibits nonvolatile memory characteristics with flexible programming/erasing operations. Furthermore, an InSe-based artificial synapse is implemented to emulate the essential synaptic functions. The pattern recognition capability of the designed artificial neural network is believed to provide an excellent paradigm for ultra-sensitive van der Waals materials to develop electric-modulated neuromorphic computation architectures.

Soluble InP and GaP nanowires: self-seeded, solution-liquid-solid synthesis and electrical properties.

A facile, self-seeded, solution-liquid-solid growth of soluble InP and GaP nanowires with a very low amount of native point defects with respect to the carrier concentrations have been synthesized (see scheme) and characterized. They are potentially promising building blocks in optoelectronic applications.We demonstrate a facile method for self-seeded, solution-liquid-solid growth of soluble InP and GaP nanowires at a temperature of approximately 300 degrees C. Both types of nanowires are single crystals with very small diameters. The synthesized InP nanowires are almost defect-free, whereas the GaP nanowires have some microtwins. The effect of reaction temperatures and input ligand/III/V (III and V indicate elements of Group 13 and 15 respectively) ratios on wire formation is discussed, and two competitive chemical pathways involved in the nanowire formation are proposed. In addition, electrical properties of these III-V nanowires, generated from the solution-based approach, were investigated for the first time. The current-voltage (I-V) and room temperature resistance investigations indicate that both InP and GaP nanowires possess very low native point defects for carrier concentrations and they could be potentially promising building blocks in optoelectronic applications.