Percolative switching in transition metal dichalcogenide field-effect transistors at room temperature.

We have addressed the microscopic transport mechanism at the switching or 'on-off' transition in transition metal dichalcogenide (TMDC) field-effect transistors (FETs), which has been a controversial topic in TMDC electronics, especially at room temperature. With simultaneous measurement of channel conductivity and its slow time-dependent fluctuation (or noise) in ultrathin WSe2 and MoS2 FETs on insulating SiO2 substrates where noise arises from McWhorter-type carrier number fluctuations, we establish that the switching in conventional backgated TMDC FETs is a classical percolation transition in a medium of inhomogeneous carrier density distribution. From the experimentally observed exponents in the scaling of noise magnitude with conductivity, we observe unambiguous signatures of percolation in a random resistor network, particularly, in WSe2 FETs close to switching, which crosses over to continuum percolation at a higher doping level. We demonstrate a powerful experimental probe to the microscopic nature of near-threshold electrical transport in TMDC FETs, irrespective of the material detail, device geometry, or carrier mobility, which can be extended to other classes of 2D material-based devices as well.

Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems.

Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.