Accelerated Single Li-Ion Transport in Solid Electrolytes for Lithium-Sulfur Batteries: Poly(Arylene Ether Sulfone) Grafted with Pyrrolidinium-Terminated Poly(Ethylene Glycol).

Polymeric solid electrolytes have attracted tremendous interest in high-safety and high-energy capacity lithium-sulfur (Li─S) batteries. There is, however, still a dilemma to concurrently attain high Li-ion conductivity and high mechanical strength that effectively suppress the Li-dendrite growth. Accordingly, a rapidly Li-ion conducting solid electrolyte is prepared by grafting pyrrolidinium cation (PYR+)-functionalized poly(ethylene glycol) onto the poly(arylene ether sulfone) backbone (PAES-g-2PEGPYR). The PYR+ groups effectively immobilize anions of Li-salts in Li-conductive PEGPYR domains phase-separated from PAES matrix to enhance the single-ion conduction. The tailored PAES-g-2PEGPYR membrane shows a high Li-ion transference number of 0.601 and superior ionic conductivity of 1.38 mS cm-1 in the flexible solid state with the tensile strength of 1.0 MPa and Young's modulus of 1.5 MPa. Moreover, this PAES-g-2PEGPYR membrane exhibits a high oxidation potential (5.5 V) and high thermal stability up to 200 (C. The Li/PAES-g-2PEGPYR/Li cell stably operates for 1000 h without any short circuit, and the rechargeable Li/PAES-g-2PEGPYR/S cell discharges a capacity of 1004.7 mAh g-1 at C/5 with the excellent rate capability and the prominent cycling performance of 95.3% retention after 200 cycles.

Electrochemical Analysis of Ion Effects on Electrolyte-Gated Synaptic Transistor Characteristics.

Electrolyte-gated transistors (EGTs) are promising candidates as artificial synapses owing to their precise conductance controllability, quick response times, and especially their low operating voltages resulting from ion-assisted signal transmission. However, it is still vague how ion-related physiochemical elements and working mechanisms impact synaptic performance. Here, to address the unclear correlations, we suggest a methodical approach based on electrochemical analysis using poly(ethylene oxide) EGTs with three alkali ions: Li+, Na+, and K+. Cyclic voltammetry is employed to identify the kind of electrochemical reactions taking place at the channel/electrolyte interface, which determines the nonvolatile memory functionality of the EGTs. Additionally, using electrochemical impedance spectroscopy and qualitative analysis of electrolytes, we confirm that the intrinsic properties of electrolytes (such as crystallinity, solubility, and ion conductivity) and ion dynamics ultimately define the linearity/symmetricity of conductance modulation. Through simple but systematic electrochemical analysis, these results offer useful insights for the selection of components for high-performing artificial synapses.

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits.

Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (∼3 × 103), wide NDT ranges (∼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.

Machine Learning Driven Channel Thickness Optimization in Dual-Layer Oxide Thin-Film Transistors for Advanced Electrical Performance.

Machine learning (ML) provides temporal advantage and performance improvement in practical electronic device design by adaptive learning. Herein, Bayesian optimization (BO) is successfully applied to the design of optimal dual-layer oxide semiconductor thin film transistors (OS TFTs). This approach effectively manages the complex correlation and interdependency between two oxide semiconductor layers, resulting in the efficient design of experiment (DoE) and reducing the trial-and-error. Considering field effect mobility (𝜇) and threshold voltage (Vth ) simultaneously, the dual-layer structure designed by the BO model allows to produce OS TFTs with remarkable electrical performance while significantly saving an amount of experimental trial (only 15 data sets are required). The optimized dual-layer OS TFTs achieve the enhanced field effect mobility of 36.1 cm2  V-1  s-1 and show good stability under bias stress with negligible difference in its threshold voltage compared to conventional IGZO TFTs. Moreover, the BO algorithm is successfully customized to the individual preferences by applying the weight factors assigned to both field effect mobility (𝜇) and threshold voltage (Vth ).