X-band MMICs for a Low-Cost Radar Transmit/Receive Module in 250 nm GaN HEMT Technology.

This paper describes Monolithic Microwave Integrated Circuits (MMICs) for an X-band radar transceiver front-end implemented in 0.25 µm GaN High Electron Mobility Transistor (HEMT) technology. Two versions of single pole double throw (SPDT) T/R switches are introduced to realize a fully GaN-based transmit/receive module (TRM), each of which achieves an insertion loss of 1.21 dB and 0.66 dB at 9 GHz, IP1dB higher than 46.3 dBm and 44.7 dBm, respectively. Therefore, it can substitute a lossy circulator and limiter used for a conventional GaAs receiver. A driving amplifier (DA), a high-power amplifier (HPA), and a robust low-noise amplifier (LNA) are also designed and verified for a low-cost X-band transmit-receive module (TRM). For the transmitting path, the implemented DA achieves a saturated output power (Psat) of 38.0 dBm and output 1-dB compression (OP1dB) of 25.84 dBm. The HPA reaches a Psat of 43.0 dBm and power-added efficiency (PAE) of 35.6%. For the receiving path, the fabricated LNA measures a small-signal gain of 34.9 dB and a noise figure of 2.56 dB, and it can endure higher than 38 dBm input power in the measurement. The presented GaN MMICs can be useful in implementing a cost-effective TRM for Active Electronically Scanned Array (AESA) radar systems at X-band.

A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS.

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is -92.6 dBc/Hz at 1-MHz and -106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is -85.2 dBc/Hz at 1-MHz offset.