Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review.

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process-Voltage-Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field.

Lightweight and Real-Time Infrared Image Processor Based on FPGA.

This paper presents an FPGA-based lightweight and real-time infrared image processor based on a series of hardware-oriented lightweight algorithms. The two-point correction algorithm based on blackbody radiation is introduced to calibrate the non-uniformity of the sensor. With precomputed gain and offset matrices, the design can achieve real-time non-uniformity correction with a resolution of 640×480. The blind pixel detection algorithm employs the first-level approximation to simplify multiple iterative computations. The blind pixel compensation algorithm in our design is constructed on the side-window-filtering method. The results of eight convolution kernels for side windows are computed simultaneously to improve the processing speed. Due to the proposed side-window-filtering-based blind pixel compensation algorithm, blind pixels can be effectively compensated while details in the image are preserved. Before image output, we also incorporated lightweight histogram equalization to make the processed image more easily observable to the human eyes. The proposed lightweight infrared image processor is implemented on Xilinx XC7A100T-2. Our proposed lightweight infrared image processor costs 10,894 LUTs, 9367 FFs, 4 BRAMs, and 5 DSP48. Under a 50 MHz clock, the processor achieves a speed of 30 frames per second at the cost of 1800 mW. The maximum operating frequency of our proposed processor can reach 186 MHz. Compared with existing similar works, our proposed infrared image processor incurs minimal resource overhead and has lower power consumption.

Design of an FPGA-Based Controller for Fast Scanning Probe Microscopy.

Atomic-scale imaging using scanning probe microscopy is a pivotal method for investigating the morphology and physico-chemical properties of nanostructured surfaces. Time resolution represents a significant limitation of this technique, as typical image acquisition times are on the order of several seconds or even a few minutes, while dynamic processes-such as surface restructuring or particle sintering, to be observed upon external stimuli such as changes in gas atmosphere or electrochemical potential-often occur within timescales shorter than a second. In this article, we present a fully redesigned field programmable gate array (FPGA)-based instrument that can be integrated into most commercially available standard scanning probe microscopes. This instrument not only significantly accelerates the acquisition of atomic-scale images by orders of magnitude but also enables the tracking of moving features such as adatoms, vacancies, or clusters across the surface ("atom tracking") due to the parallel execution of sophisticated control and acquisition algorithms and the fast exchange of data with an external processor. Each of these measurement modes requires a complex series of operations within the FPGA that are explained in detail.

Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms.

A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good performance and low energy consumption but offer customers little-to-no transparency about their internal features. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing (AxC) techniques), and design space exploration to find the optimal receiver for a use case. In this paper, we review the GNSS processing chain using SyDR, our open-source GNSS Software-Defined Radio (SDR) designed for algorithm benchmarking, and highlight the limitations of a software-only environment. In return, we propose an evolution to our system, called Hard SyDR to become closer to the hardware layer and access new Key Performance Indicator (KPI)s, such as power/energy consumption and resource utilization. We use High-Level Synthesis (HLS) and the PYNQ platform to ease our development process and provide an overview of their advantages/limitations in our project. Finally, we evaluate the foreseen developments, including how this work can serve as the foundation for an exploration of AxC techniques in future low-power GNSS receivers.

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device.

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical-star (H-star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

High Spatial Resolution Detector System Based on Reconfigurable Dual-FPGA Approach for Coincidence Measurements.

Time-resolved spectroscopic and electron-ion coincidence techniques are essential to study dynamic processes in materials or chemical compounds. For this type of analysis, it is necessary to have detectors capable of providing, in addition to image-related information, the time of arrival for each individual detected particle ("x, y, time"). The electronics capable of handling such sensors must meet requirements achievable only with time-to-digital converters (TDC) with a resolution on the order of tens of picoseconds and the use of a field-programmable gate array (FPGA) to manage data acquisition and transmission. This study introduces the design and implementation of an innovative TDC based on two FPGAs working symbiotically with different tasks: the first (AMD/Xilinx Artix® 7) directly implements a TDC, aiming for a temporal precision of 12 picoseconds, while the second (Intel Cyclone® 10) manages the acquisition and connectivity with the external world. The TDC has been optimized to operate on eight channels (+ sync) simultaneously but is potentially extendable to a greater number of channels, making it particularly suitable for coincidence measurements where it is necessary to temporally correlate multiple pieces of information from various measurement systems.

Efficient FPGA Implementation of Convolutional Neural Networks and Long Short-Term Memory for Radar Emitter Signal Recognition.

In recent years, radar emitter signal recognition has enjoyed a wide range of applications in electronic support measure systems and communication security. More and more deep learning algorithms have been used to improve the recognition accuracy of radar emitter signals. However, complex deep learning algorithms and data preprocessing operations have a huge demand for computing power, which cannot meet the requirements of low power consumption and high real-time processing scenarios. Therefore, many research works have remained in the experimental stage and cannot be actually implemented. To tackle this problem, this paper proposes a resource reuse computing acceleration platform based on field programmable gate arrays (FPGA), and implements a one-dimensional (1D) convolutional neural network (CNN) and long short-term memory (LSTM) neural network (NN) model for radar emitter signal recognition, directly targeting the intermediate frequency (IF) data of radar emitter signal for classification and recognition. The implementation of the 1D-CNN-LSTM neural network on FPGA is realized by multiplexing the same systolic array to accomplish the parallel acceleration of 1D convolution and matrix vector multiplication operations. We implemented our network on Xilinx XCKU040 to evaluate the effectiveness of our proposed solution. Our experiments show that the system can achieve 7.34 giga operations per second (GOPS) data throughput with only 5.022 W power consumption when the radar emitter signal recognition rate is 96.53%, which greatly improves the energy efficiency ratio and real-time performance of the radar emitter recognition system.

FFT-Based Simultaneous Calculations of Very Long Signal Multi-Resolution Spectra for Ultra-Wideband Digital Radio Frequency Receiver and Other Digital Sensor Applications.

The discrete Fourier transform (DFT) is the most commonly used signal processing method in modern digital sensor design for signal study and analysis. It is often implemented in hardware, such as a field programmable gate array (FPGA), using the fast Fourier transform (FFT) algorithm. The frequency resolution (i.e., frequency bin size) is determined by the number of time samples used in the DFT, when the digital sensor's bandwidth is fixed. One can vary the sensitivity of a radio frequency receiver by changing the number of time samples used in the DFT. As the number of samples increases, the frequency bin width decreases, and the digital receiver sensitivity increases. In some applications, it is useful to compute an ensemble of FFT lengths; e.g., 2P-j for j=0, 1, 2, …, J, where j is defined as the spectrum level with frequency resolution 2j·Δf. Here Δf is the frequency resolution at j=0. However, calculating all of these spectra one by one using the conventional FFT method would be prohibitively time-consuming, even on a modern FPGA. This is especially true for large values of P; e.g., P≥20. The goal of this communication is to introduce a new method that can produce multi-resolution spectrum lines corresponding to sample lengths 2P-j for all J+1 levels, concurrently, while one long 2P-length FFT is being calculated. That is, the lower resolution spectra are generated naturally as by-products during the computation of the 2P-length FFT, so there is no need to perform additional calculations in order to obtain them.

Parallelized Particle Swarm Optimization on FPGA for Realtime Ballistic Target Tracking.

This paper addresses the problem of tracking a high-speed ballistic target in real time. Particle swarm optimization (PSO) can be a solution to overcome the motion of the ballistic target and the nonlinearity of the measurement model. However, in general, particle swarm optimization requires a great deal of computation time, so it is difficult to apply to realtime systems. In this paper, we propose a parallelized particle swarm optimization technique using field-programmable gate array (FPGA) to be accelerated for realtime ballistic target tracking. The realtime performance of the proposed method has been tested and analyzed on a well-known heterogeneous processing system with a field-programmable gate array. The proposed parallelized particle swarm optimization was successfully conducted on the heterogeneous processing system and produced similar tracking results. Also, compared to conventional particle swarm optimization, which is based on the only central processing unit, the computation time is significantly reduced by up to 3.89×.

Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons.

Binary neural networks (BNNs) are variations of artificial/deep neural network (ANN/DNN) architectures that constrain the real values of weights to the binary set of numbers {-1,1}. By using binary values, BNNs can convert matrix multiplications into bitwise operations, which accelerates both training and inference and reduces hardware complexity and model sizes for implementation. Compared to traditional deep learning architectures, BNNs are a good choice for implementation in resource-constrained devices like FPGAs and ASICs. However, BNNs have the disadvantage of reduced performance and accuracy because of the tradeoff due to binarization. Over the years, this has attracted the attention of the research community to overcome the performance gap of BNNs, and several architectures have been proposed. In this paper, we provide a comprehensive review of BNNs for implementation in FPGA hardware. The survey covers different aspects, such as BNN architectures and variants, design and tool flows for FPGAs, and various applications for BNNs. The final part of the paper gives some benchmark works and design tools for implementing BNNs in FPGAs based on established datasets used by the research community.

A Self-Organizing Multi-Layer Agent Computing System for Behavioral Clustering Recognition.

Video behavior recognition often needs to focus on object motion processes. In this work, a self-organizing computational system oriented toward behavioral clustering recognition is proposed, which achieves the extraction of motion change patterns through binary encoding and completes motion pattern summarization using a similarity comparison algorithm. Furthermore, in the face of unknown behavioral video data, a self-organizing structure with layer-by-layer accuracy progression is used to achieve motion law summarization using a multi-layer agent design approach. Finally, the real-time feasibility is verified in the prototype system using real scenes to provide a new feasible solution for unsupervised behavior recognition and space-time scenes.

FPGA Implementation of Keyword Spotting System Using Depthwise Separable Binarized and Ternarized Neural Networks.

Keyword spotting (KWS) systems are used for human-machine communications in various applications. In many cases, KWS involves a combination of wake-up-word (WUW) recognition for device activation and voice command classification tasks. These tasks present a challenge for embedded systems due to the complexity of deep learning algorithms and the need for optimized networks for each application. In this paper, we propose a depthwise separable binarized/ternarized neural network (DS-BTNN) hardware accelerator capable of performing both WUW recognition and command classification on a single device. The design achieves significant area efficiency by redundantly utilizing bitwise operators in the computation of the binarized neural network (BNN) and ternary neural network (TNN). In a complementary metal-oxide semiconductor (CMOS) 40 nm process environment, the DS-BTNN accelerator demonstrated significant efficiency. Compared with a design approach where BNN and TNN were independently developed and subsequently integrated as two separate modules into the system, our method achieved a 49.3% area reduction while yielding an area of 0.558 mm2. The designed KWS system, which was implemented on a Xilinx UltraScale+ ZCU104 field-programmable gate array (FPGA) board, receives real-time data from the microphone, preprocesses them into a mel spectrogram, and uses this as input to the classifier. Depending on the order, the network operates as a BNN or a TNN for WUW recognition and command classification, respectively. Operating at 170 MHz, our system achieved 97.1% accuracy in BNN-based WUW recognition and 90.5% in TNN-based command classification.

Selective Light Measurement in the Control of Reference LED Sources.

This paper describes an original adaptive multispectral LED light source that utilizes miniature spectrometer to control its flux in real time. Current measurement of the flux spectrum is necessary in high-stability LED sources. In such cases, it is important the spectrometer work effectively with the system that controls the source and the whole system. Therefore, as important as flux stabilization is the integration of the integrating sphere-based design with the electronic module and power subsystem. Since the problem is interdisciplinary, the paper mainly focuses on presenting the solution of the flux measurement circuit. In particular, the proprietary way of operating the MEMS optical sensor as a real-time spectrometer was proposed. Then, the implementation of the sensor handling circuit, which determines the spectral measurements accuracy and thus the output flux quality, is described. Also presented is the custom method of coupling the analog part of the flux measurement path with the analog-to-digital conversion system and the control system based on the FPGA. The description of the conceptual solutions was supported by the results of simulation and laboratory tests at selected points of the measurement path. The presented concept allows to build adaptive LED light sources in the spectral range from 340 nm to 780 nm with adjustable spectrum and flux value, with electrical power up to 100 W, with adjustable flux value in the range of 100 dB, operating in constant current or pulsed mode.

sEMG-Based Hand Gesture Recognition Using Binarized Neural Network.

Recently, human-machine interfaces (HMI) that make life convenient have been studied in many fields. In particular, a hand gesture recognition (HGR) system, which can be implemented as a wearable system, has the advantage that users can easily and intuitively control the device. Among the various sensors used in the HGR system, the surface electromyography (sEMG) sensor is independent of the acquisition environment, easy to wear, and requires a small amount of data. Focusing on these advantages, previous sEMG-based HGR systems used several sensors or complex deep-learning algorithms to achieve high classification accuracy. However, systems that use multiple sensors are bulky, and embedded platforms with complex deep-learning algorithms are difficult to implement. To overcome these limitations, we propose an HGR system using a binarized neural network (BNN), a lightweight convolutional neural network (CNN), with one dry-type sEMG sensor, which is implemented on a field-programmable gate array (FPGA). The proposed HGR system classifies nine dynamic gestures that can be useful in real life rather than static gestures that can be classified relatively easily. Raw sEMG data collected from a dynamic gesture are converted into a spectrogram with information in the time-frequency domain and transferred to the classifier. As a result, the proposed HGR system achieved 95.4% classification accuracy, with a computation time of 14.1 ms and a power consumption of 91.81 mW.

FPGA Implementation of Image Registration Using Accelerated CNN.

BACKGROUND: Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention. Convolutional neural network (CNN)-based IR methods have resulted in applications that respond faster than traditional iterative IR methods. However, general-purpose processors are unable to operate at the maximum speed possible for real-time CNN algorithms. Due to its reconfigurable structure and low power consumption, the field programmable gate array (FPGA) has gained prominence for accelerating the inference phase of CNN applications. METHODS: This study proposes an FPGA-based ultrasound IR CNN (FUIR-CNN) to regress three rigid registration parameters from image pairs. To speed up the estimation process, the proposed design makes use of fixed-point data and parallel operations carried out by unrolling and pipelining techniques. Experiments were performed on three US datasets in real time using the xc7z020, and the xcku5p was also used during implementation. RESULTS: The FUIR-CNN produced results for the inference phase 139 times faster than the software-based network while retaining a negligible drop in regression performance of under 200 MHz clock frequency. CONCLUSIONS: Comprehensive experimental results demonstrate that the proposed end-to-end FPGA-based accelerated CNN achieves a negligible loss, a high speed for registration parameters, less power when compared to the CPU, and the potential for real-time medical imaging.

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method.

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.

Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking.

The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels and the I/O ports of the FPGA are connected through wire bonding within the same package. The active quenching action on each SPAD pixel is performed by using the properties of the tri-state gates of the FPGA. Digital signal processing, such as pulse counters, data encoders, and command interactions, is also performed by using the same FPGA. The breakdown voltage of the SPAD pixels, with an active area of 60 µm × 60 µm, is 47.2-48.0 V. When the device is reverse biased at a voltage of ~50.4 V, a response delay of ~50 ns, a dead time of 157 ns, a dark count rate of 2.44 kHz, and an afterpulsing probability of 6.9% are obtained. Its peak photon detection probability (PDP) reaches 17.0% at a peak wavelength of 760 nm and remains above 10% at 900 nm. This hybrid integrated SPAD array is reconfigurable and cost effective.

Oscillator Selection Strategies to Optimize a Physically Unclonable Function for IoT Systems Security.

Physically unclonable functions avoid storing secret information in non-volatile memories and only generate a key when it is necessary for an application, rising as a promising solution for the authentication of resource-constrained IoT devices. However, the need to minimize the predictability of physically unclonable functions is evident. The main purpose of this work is to determine the optimal way to construct a physically unclonable function. To do this, a ring oscillator physically unclonable function based on comparing oscillators in pairs has been implemented in an FPGA. This analysis shows that the frequencies of the oscillators greatly vary depending on their position in the FPGA, especially between oscillators implemented in different types of slices. Furthermore, the influence of the chosen locations of the ring oscillators on the quality of the physically unclonable function has been analyzed and we propose five strategies to select the locations of the oscillators. Among the strategies proposed, two of them stand out for their high uniqueness, reproducibility, and identifiability, so they can be used for authentication purposes. Finally, we have analyzed the reproducibility for the best strategy facing voltage and temperature variations, showing that it remains stable in the studied range.

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems.

The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 µs to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

FPGA Implementation of the Chirp-Scaling Algorithm for Real-Time Synthetic Aperture Radar Imaging.

Synthetic aperture radar (SAR), which can generate images of regions or objects, is an important research area of radar. The chirp scaling algorithm (CSA) is a representative SAR imaging algorithm. The CSA has a simple structure comprising phase compensation and fast Fourier transform (FFT) operations by replacing interpolation for range cell migration correction (RCMC) with phase compensation. However, real-time processing still requires many computations and a long execution time. Therefore, it is necessary to develop a hardware accelerator to improve the speed of algorithm processing. In addition, the demand for a small SAR system that can be mounted on a small aircraft or drone and that satisfies the constraints of area and power consumption is increasing. In this study, we proposed a CSA-based SAR processor that supports FFT and phase compensation operations and presents field-programmable gate array (FPGA)-based implementation results. We also proposed a modified CSA flow that simplifies the traditional CSA flow by changing the order in which the transpose operation occurs. Therefore, the proposed CSA-based SAR processor was designed to be suitable for modified CSA flow. We designed the multiplier for FFT to be shared for phase compensation, thereby achieving area efficiency and simplifying the data flow. The proposed CSA-based SAR processor was implemented on a Xilinx UltraScale+ MPSoC FPGA device and designed using Verilog-HDL. After comparing the execution times of the proposed SAR processor and the ARM cortex-A53 microprocessor, we observed a 136.2-fold increase in speed for the 4096 × 4096-pixel image.