Over 100 Million Frames per Second 368 Frames Global Shutter Burst CMOS Image Sensor with Pixel-wise Trench Capacitor Memory Array.

In this paper, a prototype ultra-high speed global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with pixel-wise trench capacitor memory array achieving over 100 million frames per second (fps) with up to 368 record length by burst correlated double sampling (CDS) operation is presented. Over 100 Mfps high frame rate is obtained by reduction of pixel output load by the pixel-wise memory array architecture and introduction of the burst CDS operation which minimizes the pixel driving pulse transitions. Long record length is realized by high density analog memory integration with Si trench capacitors. A maximum 125 Mfps frame rate with up to 368 record length video capturing was confirmed under room temperature without any cooling system. The photoelectric conversion characteristics of the burst CDS operation were measured and compared with those of the conventional CDS operation.

Nonvolatile analog memory transistor based on carbon nanotubes and C60 molecules.

A nonvolatile analog memory transistor is demonstrated by integrating C60 molecules as charge storage molecules in the transistor gate, and carbon nanotubes (CNTs) in the transistor channel. The currents through the CNT channel can be tuned quantitatively and reversibly to analog values by controlling the number of electrons trapped in the C60 molecules. After tuning, the electrons trapped in the C60 molecules in the gate, and the current through the CNT channel, can be preserved in a nonvolatile manner, indicating the characteristics of the nonvolatile analog memory.

Energy Efficient Neuro-Inspired Phase-Change Memory Based on Ge4 Sb6 Te7 as a Novel Epitaxial Nanocomposite.

Phase-change memory (PCM) is a promising candidate for neuro-inspired, data-intensive artificial intelligence applications, which relies on the physical attributes of PCM materials including gradual change of resistance states and multilevel operation with low resistance drift. However, achieving these attributes simultaneously remains a fundamental challenge for PCM materials such as Ge2 Sb2 Te5 , the most commonly used material. Here bi-directional gradual resistance changes with ≈10× resistance window using low energy pulses are demonstrated in nanoscale PCM devices based on Ge4 Sb6 Te7 , a new phase-change nanocomposite material . These devices show 13 resistance levels with low resistance drift for the first 8 levels, a resistance on/off ratio of ≈1000, and low variability. These attributes are enabled by the unique microstructural and electro-thermal properties of Ge4 Sb6 Te7 , a nanocomposite consisting of epitaxial SbTe nanoclusters within the Ge-Sb-Te matrix, and a higher crystallization but lower melting temperature than Ge2 Sb2 Te5 . These results advance the pathway toward energy-efficient analog computing using PCM.

In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory.

In-memory computing based on non-volatile resistive memory can significantly improve the energy efficiency of artificial neural networks. However, accurate in situ training has been challenging due to the nonlinear and stochastic switching of the resistive memory elements. One promising analog memory is the electrochemical random-access memory (ECRAM), also known as the redox transistor. Its low write currents and linear switching properties across hundreds of analog states enable accurate and massively parallel updates of a full crossbar array, which yield rapid and energy-efficient training. While simulations predict that ECRAM based neural networks achieve high training accuracy at significantly higher energy efficiency than digital implementations, these predictions have not been experimentally achieved. In this work, we train a 3 × 3 array of ECRAM devices that learns to discriminate several elementary logic gates (AND, OR, NAND). We record the evolution of the network's synaptic weights during parallel in situ (on-line) training, with outer product updates. Due to linear and reproducible device switching characteristics, our crossbar simulations not only accurately simulate the epochs to convergence, but also quantitatively capture the evolution of weights in individual devices. The implementation of the first in situ parallel training together with strong agreement with simulation results provides a significant advance toward developing ECRAM into larger crossbar arrays for artificial neural network accelerators, which could enable orders of magnitude improvements in energy efficiency of deep neural networks.

Non-linear Memristive Synaptic Dynamics for Efficient Unsupervised Learning in Spiking Neural Networks.

Spiking neural networks (SNNs) are a computational tool in which the information is coded into spikes, as in some parts of the brain, differently from conventional neural networks (NNs) that compute over real-numbers. Therefore, SNNs can implement intelligent information extraction in real-time at the edge of data acquisition and correspond to a complementary solution to conventional NNs working for cloud-computing. Both NN classes face hardware constraints due to limited computing parallelism and separation of logic and memory. Emerging memory devices, like resistive switching memories, phase change memories, or memristive devices in general are strong candidates to remove these hurdles for NN applications. The well-established training procedures of conventional NNs helped in defining the desiderata for memristive device dynamics implementing synaptic units. The generally agreed requirements are a linear evolution of memristive conductance upon stimulation with train of identical pulses and a symmetric conductance change for conductance increase and decrease. Conversely, little work has been done to understand the main properties of memristive devices supporting efficient SNN operation. The reason lies in the lack of a background theory for their training. As a consequence, requirements for NNs have been taken as a reference to develop memristive devices for SNNs. In the present work, we show that, for efficient CMOS/memristive SNNs, the requirements for synaptic memristive dynamics are very different from the needs of a conventional NN. System-level simulations of a SNN trained to classify hand-written digit images through a spike timing dependent plasticity protocol are performed considering various linear and non-linear plausible synaptic memristive dynamics. We consider memristive dynamics bounded by artificial hard conductance values and limited by the natural dynamics evolution toward asymptotic values (soft-boundaries). We quantitatively analyze the impact of resolution and non-linearity properties of the synapses on the network training and classification performance. Finally, we demonstrate that the non-linear synapses with hard boundary values enable higher classification performance and realize the best trade-off between classification accuracy and required training time. With reference to the obtained results, we discuss how memristive devices with non-linear dynamics constitute a technologically convenient solution for the development of on-line SNN training.