A Vertically Integrated Junctionless Nanowire Transistor.

Lee, Byung-Hyun; Hur, Jae; Kang, Min-Ho; Bang, Tewook; Ahn, Dae-Chul; Lee, Dongil; Kim, Kwang-Hee; Choi, Yang-Kyu.

Lee BH; School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Hur J; Memory Business, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, 18448, Republic of Korea.
Kang MH; School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Bang T; Department of Nano-process, National Nanofab Center (NNFC) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Ahn DC; School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Lee D; School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Kim KH; School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.
Choi YK; Department of Nano-process, National Nanofab Center (NNFC) , 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea.

Nano Lett ; 16(3): 1840-7, 2016 Mar 09.

Article en En | MEDLINE | ID: mdl-26885948

Palabras clave

Silicon nanowire (SiNW); gate-all-around (GAA); junctionless transistor; one-route all-dry etch; three-dimensional nonvolatile memory; vertical integration

Texto completo: 1 Banco de datos: MEDLINE Idioma: En Año: 2016 Tipo del documento: Article

Texto completo: 1 Banco de datos: MEDLINE Idioma: En Año: 2016 Tipo del documento: Article