Your browser doesn't support javascript.
loading
Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.
Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook.
  • Kim HM; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Kwon DW; Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720-1770, USA.
  • Kim S; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Lee K; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Lee J; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Park E; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Lee R; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Kim H; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
  • Kim S; Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, Korea.
  • Park BG; Inter-University Semiconductor Research Center (ISRC) and Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea.
J Nanosci Nanotechnol ; 18(9): 5882-5886, 2018 09 01.
Article en En | MEDLINE | ID: mdl-29677710
ABSTRACT
In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (>107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.
Texto completo
Imprimir
XML
PubMed Links
Search on Google

Texto completo: 1 Banco de datos: MEDLINE Idioma: En Año: 2018 Tipo del documento: Article
Texto completo
Imprimir
XML
PubMed Links
Search on Google

Texto completo: 1 Banco de datos: MEDLINE Idioma: En Año: 2018 Tipo del documento: Article