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A 1.8-2.7 GHz Triple-Band Low Noise Amplifier with 31.5 dB Dynamic Range of Power Gain and Adaptive Power Consumption for LTE Application.
Asl, S Ali Hosseini; Rad, Reza E; Rikan, Behnam S; Pu, YoungGun; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon.
  • Asl SAH; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
  • Rad RE; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
  • Rikan BS; SKAIChips Co., Ltd., Suwon 16419, Korea.
  • Pu Y; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
  • Hwang KC; SKAIChips Co., Ltd., Suwon 16419, Korea.
  • Yang Y; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
  • Lee KY; SKAIChips Co., Ltd., Suwon 16419, Korea.
Sensors (Basel) ; 22(11)2022 May 26.
Article en En | MEDLINE | ID: mdl-35684660
This paper presents a multi-gain radio frequency (RF) front-end low noise amplifier (LNA) utilizing a multi-core based on the source degeneration topology. The LNA can cover a wide range of input and output frequency matching by using a receiver (RX) switch at the input and a capacitor bank at the output of the LNA. In the proposed architecture here, to avoid the saturation of RX chain, 12 gain steps including positive, 0 dB, and negative power gains are controlled by a mobile industry processor interface (MIPI). The multi-core architecture offers the ability to control the power consumption over different gain steps. In order to avoid the phase discontinuity, the negative gain steps are provided using an active amplification and T-type attenuation path that keeps the phase discontinuity below ±5 degrees between two adjacent power gain steps. Using the multi-core structure, the power consumption is optimized in different power gains. The structure is enhanced with the adaptive variable cores and reactance parameters to maintain different power consumption for different gain steps and remain the output matching in an acceptable operating range. Furthermore, auxiliary linearization circuitries are added to improve the input third intercept point (IIP3) performance of the LNA. The chip is fabricated in 65 nm complementary metal-oxide semiconductor (CMOS) silicon on insulator (SOI) process and the die area is 0.308 mm2. The proposed architecture achieves the IIP3 performance of -10.2 dBm and 8.6 dBm in the highest and lowest power gains, which are 20.5 dB and -11 dB, respectively. It offers the noise figure (NF) performance of 1.15 dB in the highest power gain while it reaches 14 dB when the power gain is -11 dB. The LNA consumes 16.8 mA and 1.33 mA current from a 1 V power supply that is provided by an on-chip low-dropout (LDO) when it operates at the highest and lowest gains, respectively.
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Texto completo: 1 Banco de datos: MEDLINE Idioma: En Año: 2022 Tipo del documento: Article

Texto completo: 1 Banco de datos: MEDLINE Idioma: En Año: 2022 Tipo del documento: Article