Si/Ge Hetero Tunnel Field-Effect Transistor with Junctionless Channel Based on Nanowire.

A Si/Ge hetero tunnel field-effect transistor (TFET) with junctionless channel based on nanowire (JLNW-TFET) is proposed, and its electrical performance and dependency of natural parameters are investigated. The JLNW-TFET is operated by compensating each demerit of the following two mechanisms: thermionic generation of junctionless field-effect transistor (JLFET) and band to band tunneling (BTBT) generation of tunnel field-effect transistor (TFET). Although the on-current Ion of JLNW-TFET decreases approximately ten times as much as that of the conventional TFET, its subthreshold swing SS is three times steeper than that of the conventional TFET and ambipolar current Iambipolar does not appear as a result of the structural characteristics. Ioff increases due to Shockley-Read-Hall (SRH) recombination when the density of traps increases; however, an increase in SS is not observed. At temperatures higher than room temperature, Ioff increases slightly and SS and Ion are almost constant. Furthermore, quantum confinement and trap assisted tunneling do not significantly affect the performance of the devices except for increasing Ioff and slightly decreasing Ion.

Work-Function Engineering of Source-Overlapped Dual-Gate Tunnel Field-Effect Transistor.

A source-overlapped dual-material gate TFET (SODM-TFET), which features different materials in its source-overlapped and channel gates, is proposed here, and its performance is investigated for various channel and source gate work functions (ψmc and ψms, respectively). Previous studies reported a hump effect in source-overlapped TFETs (SO-TFETs) and relatively high currents in the ambipolar state. The flat-band voltage in our SODM-TFET was controlled by modulating ψms and ψmc, allowing to reduce the hump effect and suppressing the ambipolar current. Compared with conventional SO-TFETs, minimal subthreshold-swing (SSmin) and average SS (SSavg) of our SODM-TFET were ~4 and ~3.5 times lower, respectively. The on/off current ratio (Ion/Ioff) of the SODM-TFET increased by ~100, while the on-current (Ion) of the SODM-TFET increased by ~100 at the supply voltage of 0.7 V.

Effect of gypsum separating media on the appearance of stone cast surfaces.

STATEMENT OF PROBLEM: Several well-known parameters influence the appearance of the denture base surface, including proper isolation of the dental stone. There is lack of data describing the influence of this parameter on the appearance of the denture base surface. PURPOSE: The purpose of this study was to evaluate the effectiveness of 2 dental stone separating media on the surface of the denture base. MATERIAL AND METHODS: A conventional flasking technique for fabricating a denture base was used. Twenty casts were poured with Type III yellow dental stone to produce 20 identical denture bases. Each cast was sectioned into halves. One half of the cast was treated with Al-Cote (control group) and the other half with Iso-K separating material. Once the denture base was finished, a single examiner, blinded to the experiment, visually compared the 2 surfaces of each cast (right and left part of the cast) under natural light to determine which surface was glossier. The McNemar test (.05 significance level) was used to compare the discordant pairs (20 discordant pairs). RESULTS: Two pairs (10%) were glossier than the Iso-K treatment, and 18 pairs (90%) within the Iso-K treatment were glossier than the treatment with Al-Cote. A statistically significant difference was found between the 2 treatments (P<.001). The odds ratio was 9.00, with a 95% confidence interval of 2.155 to 79.981. CONCLUSIONS: When used according to the manufacturer's instructions, denture surfaces treated with Iso-K appeared glossier than when treated with Al-Cote separating material.

Effects of Thermal Treatment on DC Voltage-Driven Color Conversion in Organic Light-Emitting Diode.

A DC voltage-dependent color-tunable organic light-emitting diode (CTOLED) was proposed for lighting applications. The CTOLED consists of six consecutive organic layers: the hole injection layer, the hole transport layer (HTL), two emission layers (EMLs), a hole blocking layer (HBL), and an electron transport layer (ETL). Only one metal-free phthalocyanine (H2Pc) layer with a thickness of 5 nm was employed as the EML in the CTOLED on a green organic light-emitting diode (OLED) structure using tris (8-hydroxyquinoline) aluminum (III) (Alq3). The current density-voltage-luminance characteristics of the CTOLEDs before and after thermal treatment were characterized and analyzed. Several Gaussian peaks were also extracted by multipeak fitting analysis of the electroluminescent spectra. In the CTOLED before thermal treatment, green emission was dominant in the entire voltage range from low to high voltages, and blue and infrared were emitted simultaneously and at relatively low intensities at low and high voltages, respectively. In the CTOLED after thermal treatment, the dominant color conversion from blue to green was observed as the applied voltage increased, and the infrared emission was relatively low over the entire voltage range. By simulating the CTOLED with and without traps at the H2Pc interface using a technology computer-aided design simulator, we observed the following: 1. After thermal treatment, the CTOLED emitted blue light by exciton generation at the H2Pc-HBL interface because of the small electron transport through the H2Pc thin film due to the dramatic reduction of traps in the low-voltage regime. 2. In the high-voltage regime, electrons reaching the HBL were transferred to Alq3 by resonant tunneling in two quantum wells; thus, green light was emitted by exciton generation at the HTL-Alq3 interface.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter.

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

Efficacy of denture adhesives in complete denture wearers compared to denture wearers not using denture adhesives. A systematic review.

AIM: The objective of this systematic review was to evaluate the efficacy of denture adhesives (DAs) in completely edentulous denture wearers compared to not using DAs. METHODS AND RESULTS: PubMed, Web of Science, Cochrane Library, and EMBASE were searched from the database inception up to 6 February 2020 for Randomized Controlled Trials (RCTs) involving patients with complete dentures in both arches where the use of DAs was compared to no use of DAs. A total of 497 abstracts were reviewed, resulting in inclusion of 10 RCTs. Outcomes reported in the included trials were thoroughly reviewed and tabulated. The Cochrane risk of bias tool was used. All 10 studies were assessed at unclear (10%) or high risk of bias (90%). Studies showed DAs improved mainly retention/stability, and masticatory/chewing ability/performance, compared to no adhesives. CONCLUSION: Most studies showed favorable results for DAs on retention and stability of complete dentures, masticatory performance, patient's comfort and satisfaction. Due to the heterogeneity of the outcomes, unclear/high risk of bias and small sample sizes, the quality of the evidence was very low. More high-quality research is needed with improved blinding and use of standardized methods to evaluate the efficacy of DAs.

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs.

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).