Wafer-scale detachable monocrystalline germanium nanomembranes for the growth of III-V materials and substrate reuse.

Germanium (Ge) is increasingly used as a substrate for high-performance optoelectronics, photovoltaics, and electronic devices. These devices are usually grown on thick and rigid Ge substrates manufactured by classical wafering techniques. Nanomembranes (NMs) provide an alternative to this approach while offering wafer-scale lateral dimensions, weight reduction, waste limitation, and cost effectiveness. Herein, we introduce the Porous germanium Efficient Epitaxial LayEr Release (PEELER) process, which consists of the fabrication of wafer-scale detachable Ge NMs on porous Ge (PGe) and substrate reuse. We demonstrate the growth of Ge NMs with monocrystalline quality as revealed by high-resolution transmission electron microscopy (HRTEM) characterization. Together with the surface roughness below 1 nm, it makes the Ge NMs suitable for growth of III-V materials. Additionally, the embedded nanoengineered weak layer enables the detachment of the Ge NMs. Finally, we demonstrate the wet-etch-reconditioning process of the Ge substrate, allowing its reuse, to produce multiple free-standing NMs from a single parent wafer. The PEELER process significantly reduces the consumption of Ge in the fabrication process, paving the way for a new generation of low-cost flexible optoelectronic devices.

Straightforward Integration Flow of a Silicon-Containing Block Copolymer for Line-Space Patterning.

A promising alternative for the next-generation lithography is based on the directed self-assembly of block copolymers (BCPs) used as a bottom-up tool for the definition of nanometric features. Herein, a straightforward integration flow for line-space patterning is reported for a silicon BCP system, that is, poly(1,1-dimethylsilacyclobutane)-b-poly(styrene) (PDMSB-b-PS), able to define sub 15 nm features. Both in-plane cylindrical (L0 = 20.7 nm) and out-of-plane lamellar structures (L0 = 23.2 nm) formed through a rapid thermal annealing-10 min at 180 °C-were successfully integrated using graphoepitaxy to provide a long-range ordering of the BCP structure without the use of underlayers or top coats. Subsequent deep transfer into the silicon substrate using the hardened oxidized PDMSB domains as a mask is demonstrated. Combining a rapid self-assembly behavior, straightforward integration, and an excellent etching contrast, PDMSB-b-PS may become a material of choice for the next-generation lithography.

Sub-10 nm Silicon Nanopillar Fabrication Using Fast and Brushless Thermal Assembly of PS-b-PDMS Diblock Copolymer.

A new approach to obtaining spherical nanodomains using polystyrene-block-polydimethylsiloxane (PS-b-PDMS) is proposed. To reduce drastically the process time, we blended a copolymer with cylindrical morphology with a PS homopolymer. Adding PS homopolymer into a low-molar-mass cylindrical morphology PS-b-PDMS system drives it toward a spherical morphology. Besides, by controlling the as-spun state, spherical PDMS nanodomains could be kept and thermally arranged. This PS-homopolymer addition allows not only an efficient, purely thermal arrangement process of spheres but also the ability to work directly on nontreated silicon substrates. Indeed, as shown by STEM measurements, no PS brush surface treatment was necessary in our study to avoid a PDMS wetting layer at the interface with the Si substrate. Our approach was compared to a sphere-forming diblock copolymer, which needs a longer thermal annealing. Furthermore, GISAXS measurements provided complete information on PDMS sphere features. Excellent long-range order spherical microdomains were therefore produced on flat surfaces and inside graphoepitaxy trenches with a period of 21 nm, as were in-plane spheres with a diameter of 8 nm with a 15 min thermal annealing. Finally, direct plasma-etching transfer into the silicon substrate was demonstrated, and 20 nm high silicon nanopillars were obtained, which are very promising results for various nanopatterning applications.